Datasheet

(Vin ± Vout) x Vout
fsw x L x Vin
Iripple =
Iripple
2
Iload
max
= 3.15A -
Iss x tss
1.236V
Css =
LM26003
www.ti.com SNVS576D –AUGUST 2008–REVISED MARCH 2013
At very light load, in FPWM mode, the LM26003 may enter sleep mode. This is to prevent an over-voltage
condition from occurring. However, the FPWM sleep threshold is much lower than in normal operation.
ENABLE
The LM26003 provides a shutdown function via the EN pin to disable the device when the output voltage does
not need to be maintained. EN is an analog level input with typically 180 mV of hysteresis. The device is active
when the EN pin is above 1.18V (typical) and in shutdown mode when EN is below this threshold. When EN
goes high, the internal VDD regulator turns on and charges the VDD capacitor. When VDD reaches 3.9V
(typical), the soft-start pin begins to source current. In shutdown mode, the VDD regulator shuts down and total
quiescent current is reduced to 10.8 µA (typical). Because the EN pin sources 4.85 µA (typical) of pull-up current,
this pin can be left open for always-on operation. When open, EN will be pulled up to VIN.
If EN is connected to VIN, it must be connected through a 10 kΩ resistor to limit noise spikes. EN can also be
driven externally with a maximum voltage of 38V or VIN + 15V, whichever is lower.
SOFT-START
The soft-start feature provides a controlled output voltage ramp-up at startup. This reduces inrush current and
eliminates output overshoot at turn-on. The soft-start pin, SS, must be connected to GND through a capacitor. At
power-on, enable, or UVLO recovery, an internal 2.5 µA (typical) current charges the soft-start capacitor. During
soft-start, the error amplifier output voltage is controlled by both the soft-start voltage and the feedback loop. As
the SS pin voltage ramps-up, the duty-cycle increases proportional to the soft-start ramp, causing the output
voltage to ramp-up. The rate at which the duty-cycle increases depends on the capacitance of the soft-start
capacitor. The higher the capacitance, the slower the output voltage ramps-up. The soft-start capacitor value can
be calculated with the following equation:
(4)
Where tss is the desired soft-start time and Iss is the soft-start source current. During soft-start, current limit and
synchronization remain in effect, while sleep mode and frequency foldback are disabled. Soft-start mode ends
when the SS pin voltage reaches 1.23V typical. At this point, output voltage control is transferred to the FB pin
and the SS pin is discharged.
CURRENT LIMIT
The peak current limit is set internally by directly measuring peak inductor current through the internal switch. To
ensure accurate current sensing, AVIN should be bypassed with a minimum 100 nF ceramic capacitor as close
as possible to AVIN and GND pins. Also the PVIN pin should be bypassed with at least 2.2 µF to ensure low
jitter operation.
When the inductor current reaches the current limit threshold, the internal FET turns off immediately allowing
inductor current to ramp-down until the next cycle. This reduction in duty-cycle corresponds to a reduction in
output voltage.
The current limit comparator is disabled for less than 150 ns at the leading edge for increased immunity to
switching noise.
Because the current limit monitors peak inductor current, the DC load current limit threshold varies with
inductance and frequency. Assuming a minimum current limit of 3.15A, maximum load current can be calculated
as follows:
(5)
Where Iripple is the peak-to-peak inductor ripple current, calculated as shown below:
(6)
To find the worst case (lowest) current limit threshold, use the maximum input voltage and minimum current limit
specification.
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