Datasheet

Vfb
fpff =
fzff x Vout
1
2 x S x R1 x C10
fzff =
1
2 x S x fz x R5
C9 =
1
2 x S x fP
MAX
x R5
C8 =
LM26001, LM26001Q
www.ti.com SNVS430G –MAY 2006–REVISED MAY 2006
Where B is the desired feedback gain in v/v between fp and fz, and gm is the transconductance of the error
amplifier. A gain value around 10dB (3.3v/v) is generally a good starting point. Bandwidth increases with
increasing values of R5.
3. Next, place a zero (fzc) near fp using C8. C8 can be determined with the following equation:
(21)
The selected value of C8 should place fzc within a decade above or below fpmax, and not less than fpmin. A
higher C8 value (closer to fpmin) generally provides a more stable loop, but too high a value will slow the
transient response time. Conversely, a smaller C8 value will result in a faster transient response, but lower phase
margin.
4. A second pole (fpc1) can also be placed at fz. This pole can be created with a single capacitor, C9. The
minimum value for this capacitor can be calculated by:
(22)
C9 may not be necessary in all applications. However if the operating frequency is being synchronized below the
nominal frequency, C9 is recommended. Although it is not required for stability, C9 is very helpful in suppressing
noise.
A phase lead capacitor can also be added to increase the phase and gain margins. The phase lead capacitor is
most helpful for high input voltage applications or when synchronizing to a frequency greater than nominal. This
capacitor, shown as C10 in Figure 24, should be placed in parallel with the top feedback resistor, R1. C10
introduces an additional zero and pole to the compensation network. These frequencies can be calculated as
shown below:
(23)
(24)
A phase lead capacitor will boost loop phase around the region of the zero frequency, fzff. fzff should be placed
somewhat below the fpz1 frequency set by C9. However, if C10 is too large, it will have no effect.
PCB Layout
Good board layout is critical for switching regulators such as the LM26001. First, the ground plane area must be
sufficient for thermal dissipation purposes, and second, appropriate guidelines must be followed to reduce the
effects of switching noise.
Switch mode converters are very fast switching devices. In such devices, the rapid increase of input current
combined with parasitic trace inductance generates unwanted Ldi/dt noise spikes at the SW node and also at the
VIN node. The magnitude of this noise tends to increase as the output current increases. This parasitic spike
noise may turn into electromagnetic interference (EMI), and can also cause problems in device performance.
Therefore, care must be taken in layout to minimize the effect of this switching noise.
The current sensing circuit in current mode devices can be easily affected by switching noise. This noise can
cause duty cycle jitter which leads to increased spectral noise. Although the LM26001 has 100ns blanking time at
the beginning of every cycle to ignore this noise, some noise may remain after the blanking time. Following the
important guidelines below will help minimize switching noise and its effect on current sensing.
The switch node area should be as small as possible. The catch diode, input capacitors, and output capacitors
should be grounded to a large ground plane, with the bulk input capacitor grounded as close as possible to the
catch diode anode. Additionally, the ground area between the catch diode and bulk input capacitor is very noisy
and should be somewhat isolated from the rest of the ground plane.
A ceramic input capacitor must be connected as close as possible to the VIN pin and grounded close to the GND
pin. Often this capacitor is most easily located on the bottom side of the pcb. If placement close to the GND pin
is not practical, the ceramic input capacitor can also be grounded close to the catch diode ground. The above
layout recommendations are illustrated below in Figure 25.
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