Datasheet

Sync_Dmin
t
1 -
fnom
f
sync
0
50 100 150 200 250 300
R
FREQ
(k:)
100
200
300
400
500
600
SWITCHING FREQUENCY (kHz)
LM26001, LM26001Q
www.ti.com SNVS430G –MAY 2006–REVISED MAY 2006
If the FB voltage falls below the frequency foldback threshold during frequency synchronized operation, the
SYNC function is disabled. Operating frequency versus FB voltage in short circuit conditions is shown in the
Typical Performance Characteristics section.
Under conditions where the on time is close to minimum (less than 200nsec typically), such as high input voltage
and high switching frequency, the current limit may not function properly. This is because the current limit circuit
cannot reduce the on-time below minimum which prevents entry into frequency foldback mode. There are two
ways to ensure proper current limit and foldback operation under high input voltage conditions. First, the
operating frequency can be reduced to increase the nominal on time. Second, the inductor value can be
increased to slow the current ramp and reduce the peak over-current.
FREQUENCY ADJUSTMENT AND SYNCHRONIZATION
The switching frequency of the LM26001 can be adjusted between 150 kHz and 500 kHz using a single external
resistor. This resistor is connected from the FREQ pin to ground as shown in the typical application. The resistor
value can be calculated with the following empirically derived equation:
R
FREQ
= (6.25 x 10
10
) x f
SW
-1.042
(7)
Figure 19. Switching Frequency vs R
FREQ
The switching frequency can also be synchronized to an external clock signal using the SYNC pin. The SYNC
pin allows the operating frequency to be varied above and below the nominal frequency setting. The adjustment
range is from 30% above nominal to 20% below nominal. External synchronization requires a 1.2V (typical) peak
signal level at the SYNC pin. The FREQ resistor must always be connected to initialize the nominal operating
frequency. The operating frequency is synchronized to the falling edge of the SYNC input. When SYNC goes
low, the high-side switch turns on. This allows any duty cycle to be used for the sync signal when synchronizing
to a frequency higher than nominal. When synchronizing to a lower frequency, however, there is a minimum duty
cycle requirement for the SYNC signal, given in the equation below:
(8)
Where fnom is the nominal switching frequency set by the FREQ resistor, and fsync is a square wave. If the
SYNC pin is not used, it must be pulled low for normal operation. A 10kΩ pull-down resistor is recommended to
protect against a missing sync signal. Although the LM26001 is designed to operate at up to 500 kHz, maximum
load current may be limited at higher frequencies due to increased temperature rise. See the Thermal
Considerations and TSD section.
VBIAS
The VBIAS pin is used to bypass the internal regulator which provides the bias voltage to the LM26001. When
the VBIAS pin is connected to a voltage greater than 3V, the internal regulator automatically switches over to the
VBIAS input. This reduces the current into VIN (Iq) and increases system efficiency. Using the VBIAS pin has the
added benefit of reducing power dissipation within the device.
For most applications where 3V < Vout < 10V, VBIAS can be connected to Vout. If not used, VBIAS should be
tied to GND.
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