Datasheet

Vout

20 mV/Div

2V/Div

100 mA/Div

4 Ps/DIV

LM26001, LM26001Q

SNVS430G –MAY 2006–REVISED MAY 2006

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If VBIAS drops below 2.9V (typical), the device automatically switches over to supply the internal bias voltage

from Vin.

LOW VIN OPERATION AND UVLO

The LM26001 is designed to remain operational during short line transients when input voltage may drop as low

as 3.0V. Minimum nominal operating input voltage is 4.0V. Below this voltage, switch R

DS(ON)

increases, due to

the lower gate drive voltage from VDD. The minimum voltage required at VDD is approximately 3.5V for normal

operation within specification.

VDD can also be used as a pull-up voltage for functions such as PGOOD and FPWM. Note that if VDD is used

externally, the pin is not recommended for loads greater than 1 mA.

If the input voltage approaches the nominal output voltage, the duty cycle is maximized to hold up the output

voltage. In this mode of operation, once the duty cycle reaches its maximum, the LM26001 can skip a maximum

of seven off pulses, effectively increasing the duty cycle and thus minimizing the dropout from input to output.

Typical off-pulse skipping waveforms are shown in Figure 20.

Figure 20. Off-pulse Skipping Waveforms Vin = 3.5V, Vnom = 3.3V, fnom = 305kHz

UVLO is sensed at both VIN and VDD, and is activated when either voltage falls below 2.9V (typical). Although

VDD is typically less than 200mV below VIN, it will not discharge through VIN. Therefore when the VIN voltage

drops rapidly, VDD may remain high, especially in sleep mode. For fast line voltage transients, using a larger

capacitor at the VDD pin can help to hold off a UVLO shutdown by extending the VDD discharge time. By

holding up VDD, a larger cap can also reduce the R

DS(ON)

(and dropout voltage) in low VIN conditions.

Alternately, under heavy loading the VDD voltage can fall several hundred mV below VIN. In this case, UVLO

may be triggered by VDD even though the VIN voltage is above the UVLO threshold.

When UVLO is activated the LM26001 enters a standby state in which VDD remains charged. As input voltage

and VDD voltage rise above 3.9V (typical) the device will restart from softstart mode.

PGOOD

A power good pin, PGOOD, is available to monitor the output voltage status. The pin is internally connected to

an open drain MOSFET, which remains open while the output voltage is within operating range. PGOOD goes

low (low impedance to ground) when the output falls below 85% of nominal or EN is pulled low. When the output

voltage returns to within 92% of nominal, as measured at the FB pin, PGOOD returns to a high state. For

improved noise immunity, there is a 5us delay between the PGOOD threshold and the PGOOD pin going low.

Design Information

EXAMPLE CIRCUIT

Figure 21 shows a complete typical application schematic. The components have been selected based on the

design criteria given in the following sections.

Product Folder Links: LM26001 LM26001Q