Datasheet

I
Sleep
=
I
min
+ 0.13 P
Vin - Vout
L
2
x
fsw x L
D x 2 x (Vin ± Vout)
Vout
50 mV/Div
V
SW
5V/Div
IL
200 mA/Div
100 Ps/DIV
1 Ps/DIV
Vout
10 mV/Div
IL
500 mA/Div
ID
1A/Div
V
SW
5V/Div
LM26001, LM26001Q
SNVS430G –MAY 2006–REVISED MAY 2006 www.ti.com
Figure 15. PWM Waveforms 1A Load, Vin = 12V
SLEEP MODE
In light load conditions, the LM26001 automatically switches into sleep mode for improved efficiency. As loading
decreases, the voltage at FB increases and the COMP voltage decreases. When the COMP voltage reaches the
0.6V (typical) clamp threshold, and the FB voltage rises 1% above nominal, sleep mode is enabled and switching
stops. The regulator remains in sleep mode until the FB voltage falls to the reset threshold, at which point
switching resumes. This 1% FB window limits the corresponding output ripple to approximately 1% of nominal
output voltage. The sleep cycle will repeat until load current is increased. Figure 16 shows typical switching and
output voltage waveforms in sleep mode.
Figure 16. Sleep Mode Waveforms 25mA Load, Vin = 12V
In sleep mode, quiescent current is reduced to less than 40 µA when not switching. The DC sleep mode
threshold can be calculated according to the equation below:
(1)
Where Imin = Ilim/16 (2.5A/16 typically) and D = duty cycle, defined as (Vout + Vdiode)/Vin.
When load current increases above this limit, the LM26001 is forced back into normal PWM operation. The sleep
mode threshold varies with frequency, inductance, and duty cycle as shown in Figure 17.
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