Datasheet

SD/SS

LM2597

LM2597, LM2597HV

SNVS119C –MARCH 1998–REVISED APRIL 2013

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Figure 33. Timing Diagram for 5V Output

Figure 34. External 3.7V Soft-Start Clamp

DELAY CAPACITOR

DELAY

—Provides delay for the error flag output. See the upper curve in Figure 32, and also refer to timing

diagrams in Figure 33. A capacitor on this pin provides a time delay between the time the regulated output

voltage (when it is increasing in value) reaches 95% of the nominal output voltage, and the time the error flag

output goes high. A 3 μA constant current from the delay pin charges the delay capacitor resulting in a voltage

ramp. When this voltage reaches a threshold of approximately 1.3V, the open collector error flag output (or

power OK) goes high. This signal can be used to indicate that the regulated output has reached the correct

voltage and has stabilized.

If, for any reason, the regulated output voltage drops by 5% or more, the error output flag (Pin 1) immediately

goes low (internal transistor turns on). The delay capacitor provides very little delay if the regulated output is

dropping out of regulation. The delay time for an output that is decreasing is approximately a 1000 times less

than the delay for the rising output. For a 0.1 μF delay capacitor, the delay time would be approximately 50 ms

when the output is rising and passes through the 95% threshold, but the delay for the output dropping would only

be approximately 50 μs.

Pull Up

—The error flag output, (or power OK) is the collector of a NPN transistor, with the emitter internally

grounded. To use the error flag, a pullup resistor to a positive voltage is needed. The error flag transistor is rated

up to a maximum of 45V and can sink approximately 3 mA. If the error flag is not used, it can be left open.

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