Datasheet

1
2
3
4
5
6
7
8
VIN
PRE
FB
VCC
IS
AGND
OUT
RAMP
9
10
11
12
COMP
SD
BST
RT
13
14
15
16
SS
PGND
SYNC
SW
BST
SW
COMP
FB
SS
RAMP
RT
VCC
VIN
OUT
IS
GND
LM25575
VIN
VOUT
SYNC
SD
LM25575, LM25575-Q1
SNVS479G –JANUARY 2007–REVISED APRIL 2013 www.ti.com
Simplified Application Schematic
Connection Diagram
Figure 1. Top View
16-Lead HTSSOP
PIN DESCRIPTIONS
Pin(s) Name Description Application Information
1 VCC Output of the bias regulator Vcc tracks Vin up to 9V. Beyond 9V, Vcc is regulated to 7 Volts.
A 0.1uF to 1uF ceramic decoupling capacitor is required. An
external voltage (7.5V – 14V) can be applied to this pin to
reduce internal power dissipation.
2 SD Shutdown or UVLO input If the SD pin voltage is below 0.7V the regulator will be in a low
power state. If the SD pin voltage is between 0.7V and 1.225V
the regulator will be in standby mode. If the SD pin voltage is
above 1.225V the regulator will be operational. An external
voltage divider can be used to set a line undervoltage shutdown
threshold. If the SD pin is left open circuit, a 5µA pull-up current
source configures the regulator fully operational.
3 Vin Input supply voltage Nominal operating range: 6V to 42V
4 SYNC Oscillator synchronization input or output The internal oscillator can be synchronized to an external clock
with an external pull-down device. Multiple LM25575 devices
can be synchronized together by connection of their SYNC pins.
5 COMP Output of the internal error amplifier The loop compensation network should be connected between
this pin and the FB pin.
6 FB Feedback signal from the regulated output This pin is connected to the inverting input of the internal error
amplifier. The regulation threshold is 1.225V.
7 RT Internal oscillator frequency set input The internal oscillator is set with a single resistor, connected
between this pin and the AGND pin.
2 Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated
Product Folder Links: LM25575 LM25575-Q1