Datasheet

REF LEVEL
0.000 dB
0.0 deg
100 1k
START 100.000 Hz
10k
STOP 100 000.000 Hz
/DIV
10.000 dB
45.000 deg
0
GAIN
PHASE
100k
LM25575, LM25575-Q1
www.ti.com SNVS479G –JANUARY 2007–REVISED APRIL 2013
Capacitor C12 provides filtering for the divider. The voltage at the SD pin should never exceed 8V, when using
an external set-point divider it may be necessary to clamp the SD pin at high input voltage conditions. The
reference design utilizes the full range of the LM25575 (6V to 42V); therefore these components can be omitted.
With the SD pin open circuit the LM25575 responds once the Vcc UVLO threshold is satisfied.
R7, C11
A snubber network across the power diode reduces ringing and spikes at the switching node. Excessive ringing
and spikes can cause erratic operation and couple spikes and noise to the output. Voltage spikes beyond the
rating of the LM25575 or the re-circulating diode can damage these devices. Selecting the values for the snubber
is best accomplished through empirical methods. First, make sure the lead lengths for the snubber connections
are very short. For the current levels typical for the LM25575 a resistor value between 5 and 20 Ohms is
adequate. Increasing the value of the snubber capacitor results in more damping but higher losses. Select a
minimum value of C11 that provides adequate damping of the SW pin waveform at high load.
R4, C5, C6
These components configure the error amplifier gain characteristics to accomplish a stable overall loop gain. One
advantage of current mode control is the ability to close the loop with only two feedback components, R4 and C5.
The overall loop gain is the product of the modulator gain and the error amplifier gain. The DC modulator gain of
the LM25575 is as follows:
DC Gain
(MOD)
= G
m(MOD)
x R
LOAD
= 1 x R
LOAD
(13)
The dominant low frequency pole of the modulator is determined by the load resistance (R
LOAD
,) and output
capacitance (C
OUT
). The corner frequency of this pole is:
f
p(MOD)
= 1 / (2π R
LOAD
C
OUT
) (14)
For R
LOAD
= 5Ω and C
OUT
= 130µF then f
p(MOD)
= 245Hz
DC Gain
(MOD)
= 1 x 5 = 14dB
For the design example of Typical Application Circuit and Block Diagram the following modulator gain vs.
frequency characteristic was measured as shown in Figure 9.
Figure 9. Gain and Phase of Modulator R
LOAD
= 5 Ohms and C
OUT
= 130µF
Components R4 and C5 configure the error amplifier as a type II configuration which has a pole at DC and a
zero at f
Z
= 1 / (2πR4C5). The error amplifier zero cancels the modulator pole leaving a single pole response at
the crossover frequency of the loop gain. A single pole response at the crossover frequency yields a very stable
loop with 90 degrees of phase margin.
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