Datasheet

1
2
3
4
5
6
7
8
VIN
PRE
FB
VCC
IS
AGND
OUT
RAMP
9
10
11
12
COMP
SD
BST
RT
13
14
15
16
SS
PGND
SYNC
SW
LM25574, LM25574-Q1
SNVS483G –JANUARY 2007–REVISED APRIL 2013 www.ti.com
Connection Diagram
Figure 1. Top View
16-Lead TSSOP
PIN DESCRIPTIONS
Pin(s) Name Description Application Information
1 VCC Output of the bias regulator Vcc tracks Vin up to 9V. Beyond 9V, Vcc is regulated to 7 Volts.
A 0.1uF to 1uF ceramic decoupling capacitor is required. An
external voltage (7.5V – 14V) can be applied to this pin to
reduce internal power dissipation.
2 SD Shutdown or UVLO input If the SD pin voltage is below 0.7V the regulator will be in a low
power state. If the SD pin voltage is between 0.7V and 1.225V
the regulator will be in standby mode. If the SD pin voltage is
above 1.225V the regulator will be operational. An external
voltage divider can be used to set a line undervoltage shutdown
threshold. If the SD pin is left open circuit, a 5µA pull-up current
source configures the regulator fully operational.
3 Vin Input supply voltage Nominal operating range: 6V to 42V
4 SYNC Oscillator synchronization input or output The internal oscillator can be synchronized to an external clock
with an external pull-down device. Multiple LM25574 devices
can be synchronized together by connection of their SYNC pins.
5 COMP Output of the internal error amplifier The loop compensation network should be connected between
this pin and the FB pin.
6 FB Feedback signal from the regulated output This pin is connected to the inverting input of the internal error
amplifier. The regulation threshold is 1.225V.
7 RT Internal oscillator frequency set input The internal oscillator is set with a single resistor, connected
between this pin and the AGND pin.
8 RAMP Ramp control signal An external capacitor connected between this pin and the AGND
pin sets the ramp slope used for current mode control.
Recommended capacitor range 50pF to 2000pF.
9 AGND Analog ground Internal reference for the regulator control functions
10 SS Soft-start An external capacitor and an internal 10µA current source set
the time constant for the rise of the error amp reference. The SS
pin is held low during standby, Vcc UVLO and thermal
shutdown.
11 OUT Output voltage connection Connect directly to the regulated output voltage.
12 PGND Power ground Low side reference for the PRE switch and the IS sense resistor.
13 IS Current sense Current measurement connection for the re-circulating diode. An
internal sense resistor and a sample/hold circuit sense the diode
current near the conclusion of the off-time. This current
measurement provides the DC level of the emulated current
ramp.
14 SW Switching node The source terminal of the internal buck switch. The SW pin
should be connected to the external Schottky diode and to the
buck inductor.
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Product Folder Links: LM25574 LM25574-Q1