Datasheet

LM25119/25119Q
SNVS680G –AUGUST 2010–REVISED JANUARY 2014 www.ti.com
Pin Descriptions (continued)
Pin Name Description
22 PGND2 Power ground return pin for low side MOSFET gate driver. Connect directly to the low side of the
channel2 current sense resistor.
23 LO2 Low side MOSFET gate drive output. Connect to the gate of the channel2 low-side synchronous
MOSFET through a short, low inductance path.
24 VCC2 Bias supply pin. Locally decouple to PGND2 using a low ESR/ESL capacitor located as close to
controller as possible.
25 SW2 Switching node of the buck regulator. Connect to channel2 bootstrap capacitor, the source terminal of
the high-side MOSFET and the drain terminal of the low-side MOSFET.
26 HO2 High side MOSFET gate drive output. Connect to the gate of the channel2 high-side MOSFET through
a short, low inductance path.
27 HB2 High-side driver supply for bootstrap gate drive. Connect to the cathode of the channel2 external
bootstrap diode and to the bootstrap capacitor. The bootstrap capacitor supplies current to charge the
high side MOSFET gate and should be placed as close to the controller as possible.
28 UVLO Under-voltage lockout programming pin. If the UVLO pin is below 0.4 V, the regulator will be in the
shutdown mode with all function disabled. If the UVLO pin is greater than 0.4 V and below 1.25 V, the
regulator will be in standby mode with the VCC regulators operational, the SS pins grounded and no
switching at the HO and LO outputs. If the UVLO pin voltage is above 1.25 V, the SS pins are allowed
to ramp and pulse width modulated gate drive signals are delivered at the LO and HO pins. A 2 0 µA
current source is enabled when UVLO exceeds 1.25 V and flows through the external UVLO resistors
to provide hysteresis.
29 VIN Supply voltage input source for the VCC regulators.
30 HB1 High-side driver supply for bootstrap gate drive. Connect to the cathode of the channel1 external
bootstrap diode and to the bootstrap capacitor. The bootstrap capacitor supplies current to charge the
high side MOSFET gate and should be placed as close to controller as possible.
31 HO1 High side MOSFET gate drive output. Connect to the gate of the channel1 high-side MOSFET through
a short, low inductance path.
32 SW1 Switching node of the buck regulator. Connect to channel1 bootstrap capacitor, the source terminal of
the high-side MOSFET and the drain terminal of the low-side MOSFET.
EP EP Exposed pad of WQFN package. No internal electrical connections. Solder to the ground plane to
reduce thermal resistance.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings
(1)
VIN to AGND –0.3 to 45 V
SW1, SW2 to AGND –3.0 to 45 V
HB1 to SW1, HB2 to SW2 –0.3 to 15 V
VCC1, VCC2 to AGND
(2)
–0.3 to 15 V
FB1, FB2, DEMB, RES, VCCDIS, UVLO to AGND –0.3 to 15 V
HO1 to SW1, HO2 to SW2 –0.3 to HB+0.3 V
LO1, LO2 to AGND –0.3 to VCC+0.3 V
SS1, SS2 to AGND –0.3 to 7 V
EN2, RT to AGND –0.3 to 7 V
CS1, CS2, CSG1, CSG2 to AGND –0.3 V to 0.3 V
PGND to AGND –0.3 V to 0.3 V
ESD Rating HBM
(3)
2 kV
Storage Temperature –55°C to +150°C
Junction Temperature +150°C
(1) Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which
the device is intended to be functional. For specifications and test conditions see the Electrical Characteristics Table.
(2) These pins must not exceed VIN.
(3) The human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin.
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