Datasheet

LM25119/25119Q

SNVS680G –AUGUST 2010–REVISED JANUARY 2014

www.ti.com

Figure 15. 3.3 V 8 A, 1.8 V 8 A Typical Application Schematic

PCB Board Layout Recommendations

The LM25119 consists of two integrated regulators operating almost independently. Crosstalk between the two

regulators under certain conditions may be observed as switch jitter. This effect is common for any dual channel

regulator. Cross-talk effects are usually most severe when one channel is operating around 50% duty cycle.

Careful layout practices help to minimize this effect. The following board layout guidelines apply specifically to

the LM25119 and should be followed for best performance.

1. Keep the Loop1 and Loop2, shown in Figure 16, as small as possible

2. Keep the signal and power grounds separate

3. Place VCC capacitors (C6, C7) and VIN capacitor (C9) as closes as possible to the LM25119

4. Route CS and CSG traces together with Kelvin connection to the sense resistor

5. Connect AGND and PGND directly to the underside exposed pad

6. Ensure there are no high current paths beneath the underside exposed pad

Switching Jitter Root Causes and Solutions

1. Noise coupling of the high frequency switching between two channels through the input power rail

(a) Keep the high current path as short as possible

(b) Choose a FET with minimum lead inductance

IN1

, C

IN2

) as close as possible to the high-side FETs to isolate one

channel from the high frequency noise of the other channel

(d) Slow down the SW switching speed by increasing gate resistors R29 and R30

(e) Minimize the effective ESR/ESL of the input capacitor by paralleling input capacitors

2. High frequency AC noise on FB, CS, CSG and COMP

(a) Use the star ground PCB layout technique and minimize the length of the high current path

(b) Keep the signal traces away from the SW, HO, HB traces and the inductor

(d) Place CS filter capacitor (C30, C31) next to the LM25119 and on the same PCB layer as the LM25119

Product Folder Links: LM25119/25119Q