Datasheet

LM25119/25119Q

SNVS680G –AUGUST 2010–REVISED JANUARY 2014

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Figure 12. Overall Voltage Loop Gain and Phase

If a network analyzer is available, the modulator gain can be measured and the error amplifier gain can be

configured for the desired loop transfer function. If the K factor is between 2 and 3, the stability should be

checked with the network analyzer. If a network analyzer is not available, the error amplifier compensation

components can be designed with the guidelines given. Step load transient tests can be performed to verify

acceptable performance. The step load goal is minimum overshoot with a damped response. C

can be added

to the compensation network to decrease noise susceptibility of the error amplifier. The value of C

must be

sufficiently small since the addition of this capacitor adds a pole in the error amplifier transfer function. This pole

must be well beyond the loop crossover frequency. A good approximation of the location of the pole added by

is: f

= f

ZEA

x C

COMP

/ C

. The value of C

was selected as 100 pF for the design example.

Miscellaneous Functions

EN2 is left floating which allows channel2 to always remain enabled. If EN2 is pulled below 2 V, channel2 is

disabled.

The DEMB pin is left floating since this design uses diode emulation. For fully synchronous (continuous

conduction) operation, connect the DEMB to a voltage greater than 2.6 V.

VCCDIS is left floating to enable the internal VCC regulators. To disable the internal VCC regulators, connect this

pin to a voltage greater than 1.25 V.

Interleaved Operation

Interleaved operation can offer many advantages in single output, high current applications. The output power

path is split between two identical channels reducing the current in each channel by one-half. Ripple current

reduction in the output capacitors is reduced significantly since each channel operates 180 degrees out of phase

from the other. Ripple reduction is greatest at 50% duty cycle and decreases as the duty cycle varies away from

50%.

Refer to Figure 13 to estimate the ripple current reduction. Also, the effective ripple in the input and output

capacitors occurs at twice the frequency of a single channel design due to the combining of the two channels. All

of these factors are advantageous in managing the higher currents and their effects in a high power design.

Product Folder Links: LM25119/25119Q