Datasheet

LM25119/25119Q
www.ti.com SNVS680G –AUGUST 2010–REVISED JANUARY 2014
Figure 10. Modulator Gain and Phase
Components R
COMP
and C
COMP
configure the error amplifier as a Type II configuration. The DC gain of the
amplifier is 80 dB with a pole at 0 Hz and a zero at f
ZEA
= 1 / (2 π x R
COMP
x C
COMP
). The error amplifier zero
cancels the modulator pole leaving a single pole response at the crossover frequency of the voltage loop. A
single pole response at the crossover frequency yields a very stable loop with 90 degrees of phase margin. For
the design example, a conservative target loop bandwidth (crossover frequency) of 11 kHz was selected. The
compensation network zero (f
ZEA
) should be selected at least an order of magnitude less than the target
crossover frequency. This constrains the product of R
COMP
and C
COMP
for a desired compensation network zero 1
/ (2 π x R
COMP
x C
COMP
) to be about 1.1 kHz. Increasing R
COMP
, while proportionally decreasing C
COMP
, increases
the error amp gain. Conversely, decreasing R
COMP
while proportionally increasing C
COMP
, decreases the error
amp gain. For the design example C
COMP
was selected as 6800 pF and R
COMP
was selected as 36.5 kΩ. These
values configure the compensation network zero at 640 Hz. The error amp gain at frequencies greater than f
ZEA
is: R
COMP
/ R
FB2
, which is approximately 5.22 (14.3 dB).
Figure 11. Error Amplifier Gain and Phase
The overall voltage loop gain can be predicted as the sum (in dB) of the modulator gain and the error amp gain.
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