Datasheet

1
(2S x R
LOAD
x C
OUT
)
f
P(MOD)
=
R
LOAD
(A x R
S
)
DC_GAIN
(MOD)
=
P
SW
= 0.5 x V
IN
x I
O
x (t
R
+ t
F
) x f
SW
P
GC
= n x VCC x Qg x f
SW
P
DC (LO-MOSFET)
= (1 ± D) x (I
O
2
x R
DS(ON)
x 1.3)
P
DC (HO-MOSFET)
= D x (I
O
2
x R
DS(ON)
x 1.3)
LM25119/25119Q
SNVS680G –AUGUST 2010–REVISED JANUARY 2014 www.ti.com
(36)
(37)
Where, D is the duty cycle and the factor of 1.3 accounts for the increase in MOSFET on-resistance due to
heating. Alternatively, the factor of 1.3 can be eliminated and the high temperature on-resistance of the MOSFET
can be estimated using the R
DS(ON)
vs Temperature curves in the MOSFET datasheet. Gate charging loss, P
GC
,
results from the current driving the gate capacitance of the power MOSFETs and is approximated as:
(38)
Where Q
g
refers to the total gate charge of an individual MOSFET, and ‘n’ is the number of MOSFETs. Gate
charge loss differs from conduction and switching losses in that the actual dissipation occurs in the LM25119 and
not in the MOSFET itself. Further loss in the LM25119 is incurred if the gate driving current is supplied by the
internal linear regulator.
Switching loss occurs during the brief transition period as the MOSFET turns on and off. During the transition
period both current and voltage are present in the channel of the MOSFET. The switching loss can be
approximated as:
(39)
Where t
R
and t
F
are the rise and fall times of the MOSFET. The rise and fall times are usually mentioned in the
MOSFET datasheet or can be empirically observed with an oscilloscope. Switching loss is calculated for the
high-side MOSFET only. Switching loss in the low-side MOSFET is negligible because the body diode of the low-
side MOSFET turns on before the MOSFET itself, minimizing the voltage from drain to source before turn-on. For
this example, the maximum drain-to-source voltage applied to either MOSFET is 36 V.The selected MOSFETs
must be able to withstand 36 V plus any ringing from drain to source, and be able to handle at least the VCC
voltage plus any ringing from gate to source. A good choice of MOSFET for the 36 V input design example is the
SI7884. It has an R
DS(ON)
of 7.5 mΩ and total gate charge of 21 nC. In applications where a high step-down ratio
is maintained in normal operation, efficiency may be optimized by choosing a high-side MOSFET with lower Q
g
,
and low-side MOSFET with lower R
DS(ON)
.
MOSFET SNUBBER
A resistor-capacitor snubber network across the low-side MOSFET reduces ringing and spikes at the switching
node. Excessive ringing and spikes can cause erratic operation and couple noise to the output. Selecting the
values for the snubber is best accomplished through empirical methods. First, make sure the lead lengths for the
snubber connections are very short. Start with a resistor value between 5 and 50 Ω. Increasing the value of the
snubber capacitor results in more damping, but higher snubber losses. Select a minimum value for the snubber
capacitor that provides adequate damping of the spikes on the switch waveform at high load. A snubber may not
be necessary with an optimized layout.
ERROR AMPLIFIER COMPENSATION
R
COMP
, C
COMP
and C
HF
configure the error amplifier gain characteristics to accomplish a stable voltage loop gain.
One advantage of current mode control is the ability to close the loop with only two feedback components, R
COMP
and C
COMP
. The voltage loop gain is the product of the modulator gain and the error amplifier gain. For the 3.3 V
output design example, the modulator is treated as an ideal voltage-to-current converter. The DC modulator gain
of the LM25119 can be modeled as:
(40)
Note that A is the gain of the current sense amplifier which is 10 in the LM25119. The dominant low frequency
pole of the modulator is determined by the load resistance (R
LOAD
) and output capacitance (C
OUT
). The corner
frequency of this pole is:
(41)
For R
LOAD
= 3.3 V / 8 A = 0.413 Ω and C
OUT
= 724 μF (effective) then f
P(MOD)
= 532 Hz
DC Gain
(MOD)
= 0.413 Ω / (10 x 8 mΩ) = 5.16 = 14.2 dB
For the 3.3 V design example, the modulator gain vs. frequency characteristic is shown in Figure 10.
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