Datasheet
SW
CURRENT LIMIT
COMPARATOR
CS
RAMP
CLK
CSG
+
-
+
-
1.2V
CURRENT SENSE
AMPLIFIER
A=10
HO
C
RAMP
R
RAMP
R
S
I
L
L
10 x R
S
x K x R
RAMP
C
RAMP
=
V
IN
x t
PERIOD
V
RAMP
R
RAMP
x C
RAMP
LM25119/25119Q
SNVS680G –AUGUST 2010–REVISED JANUARY 2014
www.ti.com
(4)
The approximation is the first order term in a Taylor Series expansion of the exponential and is valid since t
PERIOD
is small relative to the RAMP pin R-C time constant.
Multiplying (2) by t
PERIOD
to convert the slope to a peak voltage, and then equating (2) with (4) allows us to solve
for C
RAMP
:
(5)
Choose either C
RAMP
or R
RAMP
and use (5) to calculate the other component.
The difference between the average inductor current and the DC value of the sampled inductor current can
cause instability for certain operating conditions. This instability is known as sub-harmonic oscillation, which
occurs when the inductor ripple current does not return to its initial value by the start of next switching cycle.
Sub-harmonic oscillation is normally characterized by alternating wide and narrow pulses at the switch node. The
ramp equation above contains the optimum amount of slope compensation, however extra slope compensation is
easily added by selecting a lower value for R
RAMP
or C
RAMP
.
Current Limit
The LM25119 contains a current limit monitoring scheme to protect the regulator from possible over-current
conditions. When set correctly, the emulated current signal is proportional to the buck switch current with a scale
factor determined by the current limit sense resistor, R
S
, and current sense amplifier gain. The emulated signal is
applied to the current limit comparator. If the emulated ramp signal exceeds 1.2 V, the present cycle is
terminated (cycle-by-cycle current limiting). Shown in Figure 5 is the current limit comparator and a simplified
current measurement schematic. In applications with small output inductance and high input voltage, the switch
current may overshoot due to the propagation delay of the current limit comparator. If an overshoot should occur,
the sample-and-hold circuit will detect the excess recirculating current before the buck switch is turned on again.
If the sample-and-hold DC level exceeds the internal current limit threshold, the buck switch will be disabled and
skip pulses until the current has decayed below the current limit threshold. This approach prevents current
runaway conditions due to propagation delays or inductor saturation since the inductor current is forced to decay
to a controlled level following any current overshoot.
Figure 5. Current Limit and Ramp Circuit
Hiccup Mode Current Limiting
To further protect the regulator during prolonged current limit conditions, an internal counter counts the PWM
clock cycles during which cycle-by-cycle current limiting occurs. When the counter detects 256 consecutive
cycles of current limiting, the regulator enters a low power dissipation hiccup mode with the HO and LO outputs
disabled. The restart timer pin, RES, and an external capacitor configure the hiccup mode current limiting. A
capacitor on the RES pin (C
RES
) determines the time the controller will remain in low power standby mode before
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