Datasheet

t
PERIOD
V
RAMP
= V
IN
x (1 - e
)
R
RAMP
x C
RAMP
=
L
10 x K x V
IN
x R
S
dt
dV
RAMP
RAMP
Sample and
Hold DC Level
VIN x t
ON
10 x R
S
V/A
t
ON
R
RAMP
x C
RAMP
RAMP =
LM25119/25119Q
www.ti.com SNVS680G –AUGUST 2010–REVISED JANUARY 2014
configuring the controller as a two channel, single output interleaved regulator. For these applications, the
channel1 error amplifier (FB1, COMP1) is configured as the master error amplifier. The channel2 error amplifier
must be disabled by connecting the FB2 pin to the VCC2 pin. When configured in this manner the output of the
channel2 error amplifier (COMP2) will be disabled and have a high output impedance. To complete the
interleaved configuration the COMP1 and the COMP2 pins should be connected together to facilitate PWM
control of channel2 and current sharing between channels.
Ramp Generator
The ramp signal used in the pulse width modulator for current mode control is typically derived directly from the
buck switch current. This switch current corresponds to the positive slope portion of the inductor current. Using
this signal for the PWM ramp simplifies the control loop transfer function to a single pole response and provides
inherent input voltage feed-forward compensation. The disadvantage of using the buck switch current signal for
PWM control is the large leading edge spike due to circuit parasitics that must be filtered or blanked. Also, the
current measurement may introduce significant propagation delays. The filtering, blanking time and propagation
delay limit the minimum achievable pulse width. In applications where the input voltage may be relatively large in
comparison to the output voltage, controlling small pulse widths and duty cycles are necessary for regulation.
The LM25119 utilizes a unique ramp generator which does not actually measure the buck switch current but
rather reconstructs the signal. Representing or emulating the inductor current provides a ramp signal to the PWM
comparator that is free of leading edge spikes and measurement or filtering delays. The current reconstruction is
comprised of two elements; a sample-and-hold DC level and the emulated inductor current ramp as shown in
Figure 4.
Figure 4. Composition of Current Sense Signal
The sample-and-hold DC level is derived from a measurement of the recirculating current flowing through the
current sense resistor. The voltage across the sense resistor is sampled and held just prior to the onset of the
next conduction interval of the buck switch. The current sensing and sample-and-hold provide the DC level of the
reconstructed current signal. The positive slope inductor current ramp is emulated by an external capacitor
connected from RAMP pin to AGND and a series resistor connected between SW and RAMP. The ramp resistor
should not be connected to VIN directly because the RAMP pin voltage rating could be exceeded under high VIN
conditions. The ramp created by the external resistor and capacitor will have a slope proportional to the rising
inductor current plus some additional slope required for slope compensation. Connecting the RAMP pin resistor
to SW provides optimum slope compensation with a RAMP capacitor slope that is proportional to VIN. This
“adaptive slope compensation” eliminates the requirement for additional slope compensation circuitry with high
output voltage set points and frees the user from additional concerns in this area. The emulated ramp signal is
approximately linear and the ramp slope is given by:
(2)
The factor of 10 in equation (2) corresponds to the internal current sense amplifier gain of the LM25119. The K
factor is a constant which adds additional slope for robust pulse-width modulation control at lower input voltages.
In practice this constant can be varied from 1 to 3. R
S
is the external sense resistor value.
The voltage on the ramp capacitor is given by:
(3)
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