Datasheet

5.2 x 10
9
R
T
=
- 948
f
SW
LM25119/25119Q
SNVS680G –AUGUST 2010–REVISED JANUARY 2014 www.ti.com
In high voltage applications extra care should be taken to ensure the VIN pin does not exceed the absolute
maximum voltage rating of 45 V. During line or load transients, voltage ringing on the VIN line that exceeds the
Absolute Maximum Rating can damage the IC. Both careful PC board layout and the use of quality bypass
capacitors located close to the VIN and AGND pins are essential.
UVLO
The LM25119 contains a dual level under-voltage lockout (UVLO) circuit. When the UVLO pin is less than 0.4 V,
the LM25119 is in shutdown mode. The shutdown comparator provides 100 mV of hysteresis to avoid chatter
during transitions. When the UVLO pin voltage is greater than 0.4 V but less than 1.25 V, the controller is in
standby mode. In the standby mode the VCC bias regulators are active but the controller outputs are disabled.
This feature allows the UVLO pin to be used as a remote enable/disable function. When the VCC outputs exceed
their respective under-voltage thresholds (4 V) and the UVLO pin voltage is greater than 1.25 V, the outputs are
enabled and normal operation begins.
An external set-point voltage divider from the VIN to GND is used to set the minimum VIN operating voltage of
the regulator. The divider must be designed such that the voltage at the UVLO pin will be greater than 1.25 V
when the input voltage is in the desired operating range. UVLO hysteresis is accomplished with an internal 20 μA
current source that is switched on or off into the impedance of the set-point divider. When the UVLO pin voltage
exceeds 1.25 V threshold, the current source is activated to quickly raise the voltage at the UVLO pin. When the
UVLO pin voltage falls below the 1.25 V threshold, the current source is turned off causing the voltage at the
UVLO pin to quickly fall. The UVLO pin should not be left floating.
Enable 2
The LM25119 contains an enable function allowing shutdown control of channel2, independent of channel1. If
the EN2 pin is pulled below 2.0 V, channel2 enters shutdown mode. If the EN2 input is greater than 2.5 V,
channel2 returns to normal operation. An internal 50 kΩ pull-up resistor on the EN2 pin allows this pin to be left
floating for normal operation. The EN2 input can be used in conjunction with the UVLO pin to sequence the two
regulator channels. If EN2 is held low as the UVLO pin increases to a voltage greater than the 1.25 V UVLO
threshold, channel1 will begin operation while channel2 remains off. Both channels become operational when the
UVLO, EN2, VCC1, and VCC2 pins are above their respective operating thresholds. Either channel of the
LM25119 can also be disabled independently by pulling the corresponding SS pin to AGND.
Oscillator and Sync Capability
The LM25119 switching frequency is set by a single external resistor connected between the RT pin and the
AGND pin (R
T
). The resistor should be located very close to the device and connected directly to the pins of the
IC (RT and AGND). To set a desired switching frequency (f
SW
) of each channel, the resistor can be calculated
from the following equation:
(1)
Where RT is in ohms and f
SW
is in Hertz. The frequency f
SW
is the output switching frequency of each channel.
The internal oscillator runs at twice the switching frequency and an internal frequency divider interleaves the two
channels with 180° phase shift between PWM pulses at the HO pins.
The RT pin can be used to synchronize the internal oscillator to an external clock. The internal oscillator can be
synchronized by AC coupling a positive edge into the RT pin. The voltage at the RT pin is nominally 1.25 V and
the voltage at the RT pin must exceed 4 V to trip the internal synchronization pulse detector. A 5 V amplitude
signal and 100 pF coupling capacitor are recommended. Synchronizing at greater than twice the free-running
frequency may result in abnormal behavior of the pulse width modulator. Also, note that the output switching
frequency of each channel will be one-half the applied synchronization frequency.
Error Amplifiers and PWM Comparators
Each of the two internal high-gain error amplifiers generates an error signal proportional to the difference
between the regulated output voltage and an internal precision reference (0.8 V). The output of each error
amplifier is connected to the COMP pin allowing the user to provide loop compensation components. Generally a
Type II network is recommended. This network creates a pole at 0 Hz, a mid-band zero, and a noise reducing
high frequency pole. The PWM comparator compares the emulated current sense signal from the RAMP
generator to the error amplifier output voltage at the COMP pin. Only one error amplifier is required when
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