Datasheet

VIN
RT
RES
UVLO
VCC2
FB2
SS2
0.8V
HB2
HO2
SW2
DISABLE
LO2
VCC2
DRIVER
DRIVER
CS2
A = 10
CLK 2
RAMP2
PGND2
COMP2
CSG2
EN2
AGND
VCC DISABLE
LOGIC
CHANNEL 2
HB
UVLO
LEVEL SHIFT/
ADAPTIVE
TIMER
+
-
TRACK
SAMPLE
and
HOLD
EN2
LOGIC
S
R
Q
Q
CLK 2
+
-
+
-
-+
+
+
-
1.2V
10 PA
VCC
UVLO
7.6V
REGULATOR
VIN
1.2V
VCC1
FB1
SS1
0.8V
HB1
HO1
SW1
DISABLE
LO1
VCC1
DRIVER
DRIVER
CS1
A = 10
CLK 1
RAMP1
PGND1
COMP1
CSG1
LOGIC DECODER/
DIODE EMULATION
HB
UVLO
LEVEL SHIFT/
ADAPTIVE
TIMER
+
-
TRACK
SAMPLE
and
HOLD
S
R
Q
Q
CLK 1
+
-
+
-
-+
+
+
-
1.2V
10 PA
VCC
UVLO
7.6V
REGULATOR
VIN
1.2V
CHANNEL 1
COMMON BIAS
GENERATOR
BIAS
0.8V
UVLO
LOGIC
SHUTDOWN
STANDBY
CONTROL
THERMAL
SHUTDOWN
CHANNEL 1
CHANNEL 2
50 k:
VCCDIS
DEMB
VCC DISABLE
LOGIC
VCC
REGULATORS
LOGIC
DECODER
CHANNEL 1
CHANNEL 2
500 k:
50 k:
OSCILLATOR /
SYNC DETECTOR
CLK 1
CLK 2
10 PA
RESTART
LOGIC
HICCUP
FAULT TIMER
256 CYCLES
CHANNEL 1
STANDBY
CHANNEL 2
STANDBY
CHANNEL 1
FAULT
CHANNEL 2
FAULT
COMMON
LOGIC DECODER/
DIODE EMULATION
VCC DISABLE
LOGIC
RES Current
SS1 Current
SS2 Current
LM25119/25119Q
SNVS680G –AUGUST 2010–REVISED JANUARY 2014 www.ti.com
Block Diagram
Figure 2. Block Diagram
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Product Folder Links: LM25119/25119Q