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OUT2

SS2RESRTAGND SS1

UVLO

COMP2

FB2

OUT1

RAMP2

PGND2

CSG2

CS2

LO2

SW2

HO2

HB2

VCC2

VIN

LM25119

COMP1

FB1

RAMP1

PGND1

CSG1

CS1

LO1

SW1

HO1

HB1

VCC1

LM25119/25119Q

www.ti.com

SNVS680G –AUGUST 2010–REVISED JANUARY 2014

LM25119/LM25119Q Wide Input Range Dual Synchronous Buck Controller

Check for Samples: LM25119/25119Q

FEATURES

DESCRIPTION

• LM25119Q is an Automotive Grade product

The LM25119 is a dual synchronous buck controller

that is AEC-Q100 grade 1 qualified (-40°C to

intended for step-down regulator applications from a

125°C operating junction temperature).

high voltage or widely varying input supply. The

• Emulated peak current mode control

control method is based upon current mode control

• Wide operating range from 4.5 V to 42 V

utilizing an emulated current ramp. Current mode

control provides inherent line feed-forward, cycle-by-

• Easily configurable for dual outputs or

cycle current limiting and ease of loop compensation.

interleaved single output

The use of an emulated control ramp reduces noise

• Robust 3.3 A peak gate drive

sensitivity of the pulse-width modulation circuit,

• Switching frequency programmable to 750 kHz

allowing reliable control of very small duty cycles

necessary in high input voltage applications. The

• Optional diode emulation mode

switching frequency is programmable from 50 kHz to

• Programmable output from 0.8 V

750 kHz. The LM25119 drives external high-side and

• Precision 1.5% voltage reference

low-side NMOS power switches with adaptive dead-

time control. A user-selectable diode emulation mode

• Programmable current limit

enables discontinuous mode operation for improved

• Hiccup mode overload protection

efficiency at light load conditions. A high voltage bias

• Programmable soft-start

regulator with automatic switch-over to external bias

further improves efficiency. Additional features

• Programmable line under-voltage lockout

include thermal shutdown, frequency synchronization,

• Automatic switch-over to external bias supply

cycle-by-cycle and hiccup mode current limit and

• Channel2 enable logic input

adjustable line under-voltage lockout. The device is

available in a power enhanced leadless WQFN-32

• Thermal Shutdown

package featuring an exposed die attach pad to aid

• Leadless WQFN-32 (5 mm x 5 mm) package

thermal dissipation.

Typical Application Circuit

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (34 pages)

PAGE 1
LM25119/25119Q www.ti.com SNVS680G – AUGUST 2010 – REVISED JANUARY 2014 LM25119/LM25119Q Wide Input Range Dual Synchronous Buck Controller Check for Samples: LM25119/25119Q FEATURES 1 • 2 • • • • • • • • • • • • • • • • DESCRIPTION LM25119Q is an Automotive Grade product that is AEC-Q100 grade 1 qualified (-40°C to 125°C operating junction temperature). Emulated peak current mode control Wide operating range from 4.
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LM25119/25119Q SNVS680G – AUGUST 2010 – REVISED JANUARY 2014 www.ti.com SW1 HO1 HB1 VIN UVLO HB2 HO2 SW2 Connection Diagram 32 31 30 29 28 27 26 25 VCC1 1 24 VCC2 LO1 2 23 LO2 PGND1 3 22 PGND2 CSG1 4 21 CSG2 CS1 5 20 CS2 RAMP1 6 19 RAMP2 SS1 7 18 SS2 VCCDIS 8 17 DEMB 10 11 12 13 14 15 16 EN2 AGND RT RES COMP2 FB2 FB1 9 COMP1 Exposed Pad on Bottom Connect to Ground Figure 1.
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LM25119/25119Q www.ti.com SNVS680G – AUGUST 2010 – REVISED JANUARY 2014 Pin Functions Pin Descriptions Pin Name Description 1 VCC1 Bias supply pin. Locally decouple to PGND1 using a low ESR/ESL capacitor located as close to controller as possible. 2 LO1 Low side MOSFET gate drive output. Connect to the gate of the channel1 low-side synchronous MOSFET through a short, low inductance path. 3 PGND1 Power ground return pin for low side MOSFET gate driver.
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LM25119/25119Q SNVS680G – AUGUST 2010 – REVISED JANUARY 2014 www.ti.com Pin Descriptions (continued) Pin Name 22 PGND2 Description Power ground return pin for low side MOSFET gate driver. Connect directly to the low side of the channel2 current sense resistor. 23 LO2 Low side MOSFET gate drive output. Connect to the gate of the channel2 low-side synchronous MOSFET through a short, low inductance path. 24 VCC2 Bias supply pin.
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LM25119/25119Q www.ti.com Operating Ratings SNVS680G – AUGUST 2010 – REVISED JANUARY 2014 (1) VIN 4.5 V to 42 V VCC 4.5 V to 14 V HB to SW 4.5 V to 14 V Junction Temperature (1) –40°C to +125°C Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional. For specifications and test conditions see the Electrical Characteristics Table.
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LM25119/25119Q SNVS680G – AUGUST 2010 – REVISED JANUARY 2014 www.ti.com Electrical Characteristics Limits in standard type are for TJ = 25°C only; limits in boldface type apply over the junction temperature range of –40°C to +125°C. Unless otherwise specified, the following conditions apply: VIN = 12 V, VCC = 8 V, VCCDIS = 0 V, EN2 = 5 V, RT = 25 kΩ, no load on LO and HO. Electrical characteristics are per channel where applicable. See (1), (2), and (3).
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LM25119/25119Q www.ti.com SNVS680G – AUGUST 2010 – REVISED JANUARY 2014 Electrical Characteristics (continued) Limits in standard type are for TJ = 25°C only; limits in boldface type apply over the junction temperature range of –40°C to +125°C. Unless otherwise specified, the following conditions apply: VIN = 12 V, VCC = 8 V, VCCDIS = 0 V, EN2 = 5 V, RT = 25 kΩ, no load on LO and HO. Electrical characteristics are per channel where applicable. See (1), (2), and (3).
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LM25119/25119Q SNVS680G – AUGUST 2010 – REVISED JANUARY 2014 www.ti.
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LM25119/25119Q www.ti.
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LM25119/25119Q SNVS680G – AUGUST 2010 – REVISED JANUARY 2014 www.ti.com Block Diagram COMMON VIN CLK 1 COMMON BIAS GENERATOR RT OSCILLATOR / SYNC DETECTOR CLK 2 BIAS 0.
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LM25119/25119Q www.ti.com SNVS680G – AUGUST 2010 – REVISED JANUARY 2014 Detailed Operating Description The LM25119 high voltage switching regulator features all of the functions necessary to implement an efficient dual channel buck regulator that operates over a very wide input voltage range. The LM25119 may be configured as two independent regulators or as a single high current regulator with two interleaved channels.
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LM25119/25119Q SNVS680G – AUGUST 2010 – REVISED JANUARY 2014 www.ti.com In high voltage applications extra care should be taken to ensure the VIN pin does not exceed the absolute maximum voltage rating of 45 V. During line or load transients, voltage ringing on the VIN line that exceeds the Absolute Maximum Rating can damage the IC. Both careful PC board layout and the use of quality bypass capacitors located close to the VIN and AGND pins are essential.
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LM25119/25119Q www.ti.com SNVS680G – AUGUST 2010 – REVISED JANUARY 2014 configuring the controller as a two channel, single output interleaved regulator. For these applications, the channel1 error amplifier (FB1, COMP1) is configured as the master error amplifier. The channel2 error amplifier must be disabled by connecting the FB2 pin to the VCC2 pin. When configured in this manner the output of the channel2 error amplifier (COMP2) will be disabled and have a high output impedance.
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LM25119/25119Q SNVS680G – AUGUST 2010 – REVISED JANUARY 2014 VRAMP www.ti.com VIN x tPERIOD RRAMP x CRAMP (4) The approximation is the first order term in a Taylor Series expansion of the exponential and is valid since tPERIOD is small relative to the RAMP pin R-C time constant.
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LM25119/25119Q www.ti.com SNVS680G – AUGUST 2010 – REVISED JANUARY 2014 automatically restarting. A 10 µA current source charges the RES pin capacitor to the 1.25 V threshold which restarts the overloaded channel. The two regulator channels operate independently. One channel may operate normally while the other is in the hiccup mode overload protection. The hiccup mode commences when either channel experiences 256 consecutive PWM cycles with cycle-by-cycle current limiting.
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LM25119/25119Q SNVS680G – AUGUST 2010 – REVISED JANUARY 2014 www.ti.com Maximum Duty Cycle When operating with a high PWM duty cycle, the buck switch will be forced off each cycle for 320ns to ensure the boot-strap capacitor is recharged and to allow time to sample and hold the current in the low side MOSFET. This forced off-time limits the maximum duty cycle of the controller.
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LM25119/25119Q www.ti.com SNVS680G – AUGUST 2010 – REVISED JANUARY 2014 TIMING RESISTOR RT sets the switching frequency of each regulator channel. Generally, higher frequency applications are smaller but have higher losses. Operation at 230 kHz was selected for this example as a reasonable compromise between small size and high efficiency. The value of RT for 230 kHz switching frequency can be calculated as follows: RT = 5.2 x 10 9 fSW - 948 = 21.66 k: (7) A standard value or 22.
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LM25119/25119Q SNVS680G – AUGUST 2010 – REVISED JANUARY 2014 www.ti.com CURRENT SENSE RESISTOR Before determining the value of current sense resistor (RS), it is valuable to understand the K factor, which is the ramp slope multiple chosen for slope compensation. The K factor can be varied from 1 to 3 in practice and is defined as: K= L 10 x RS x RRAMP x CRAMP (12) The performance of the converter will vary depending on the selected K value (See Table 1).
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LM25119/25119Q www.ti.com SNVS680G – AUGUST 2010 – REVISED JANUARY 2014 OUTPUT CAPACITORS The output capacitors smooth the inductor ripple current and provide a source of charge during transient loading conditions. For this design example, a 680 µF electrolytic capacitor with 10 mΩ ESR was selected as the main output capacitor. The fundamental component of the output ripple voltage is approximated as: 'VOUT = IPP x 2 ESR + 'VOUT = 1.
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LM25119/25119Q SNVS680G – AUGUST 2010 – REVISED JANUARY 2014 ZIN = VIN www.ti.com 2 POUT (28) The damping factor for the input filter is given by: G= 1 § RIN + ESR ZS · + x 2 ¨ ZS ZIN ¸ © ¹ (29) Where RIN is the input wiring resistance and ESR is the equivalent series resistance of the input capacitors. When δ = 1, the input filter is critically damped. This may be difficult to achieve with practical component values. With δ < 0.2, the input filter will exhibit significant ringing.
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LM25119/25119Q www.ti.com SNVS680G – AUGUST 2010 – REVISED JANUARY 2014 2.21 kΩ was chosen for RFB1 in this design which results in a RFB2 value of 6.98 kΩ for VOUT1 of 3.3 V. A reasonable guide is to select the value of RFB1 in the range between 500 Ω and 10 kΩ. The value of RFB1 should be large enough to keep the total divider power dissipation small. VOUT LM25119 0.8V RFB2 FB RCOMP + COMP CCOMP RFB1 CHF Figure 8. Feedback Configuration UVLO DIVIDER The UVLO threshold is internally set to 1.
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LM25119/25119Q SNVS680G – AUGUST 2010 – REVISED JANUARY 2014 www.ti.com PDC (HO-MOSFET) = D x (IO2 x RDS(ON) x 1.3) (36) 2 PDC (LO-MOSFET) = (1 ± D) x (IO x RDS(ON) x 1.3) (37) Where, D is the duty cycle and the factor of 1.3 accounts for the increase in MOSFET on-resistance due to heating. Alternatively, the factor of 1.3 can be eliminated and the high temperature on-resistance of the MOSFET can be estimated using the RDS(ON) vs Temperature curves in the MOSFET datasheet.
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LM25119/25119Q www.ti.com SNVS680G – AUGUST 2010 – REVISED JANUARY 2014 Figure 10. Modulator Gain and Phase Components RCOMP and CCOMP configure the error amplifier as a Type II configuration. The DC gain of the amplifier is 80 dB with a pole at 0 Hz and a zero at fZEA = 1 / (2 π x RCOMP x CCOMP). The error amplifier zero cancels the modulator pole leaving a single pole response at the crossover frequency of the voltage loop.
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LM25119/25119Q SNVS680G – AUGUST 2010 – REVISED JANUARY 2014 www.ti.com Figure 12. Overall Voltage Loop Gain and Phase If a network analyzer is available, the modulator gain can be measured and the error amplifier gain can be configured for the desired loop transfer function. If the K factor is between 2 and 3, the stability should be checked with the network analyzer. If a network analyzer is not available, the error amplifier compensation components can be designed with the guidelines given.
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LM25119/25119Q www.ti.com SNVS680G – AUGUST 2010 – REVISED JANUARY 2014 Figure 13. Cancellation Factor vs. Duty Cycle for Output Capacitor To begin an interleaved design, use the previous equations in this datasheet to first calculate the required value of components using one-half the current in the output power path. The Attenuation Factor in Figure 13 is the ratio of the output capacitor ripple to the inductor ripple vs. duty cycle.
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LM25119/25119Q SNVS680G – AUGUST 2010 – REVISED JANUARY 2014 www.ti.com Figure 15. 3.3 V 8 A, 1.8 V 8 A Typical Application Schematic PCB Board Layout Recommendations The LM25119 consists of two integrated regulators operating almost independently. Crosstalk between the two regulators under certain conditions may be observed as switch jitter. This effect is common for any dual channel regulator. Cross-talk effects are usually most severe when one channel is operating around 50% duty cycle.
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LM25119/25119Q www.ti.com SNVS680G – AUGUST 2010 – REVISED JANUARY 2014 3. Ground offset at the switching frequency (a) Use the star ground PCB layout technique and minimize the length between the grounds of CIN1and CIN2 VIN CIN1 CIN2 Loop1 PGND2 CSG1 CS1 COUT2 CSG2 CS2 EP AGND RFB2A RFB1A VOUT2 PGND1 COUT1 VOUT1 Loop2 RFB1B RFB2B The bold lines indicate a solid ground plane. Make the traces to the widest and the shortest and use the star ground technique.
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LM25119/25119Q SNVS680G – AUGUST 2010 – REVISED JANUARY 2014 www.ti.com Changes from Revision F (February 2013) to Revision G • 28 Page Changed LLP-32 to WQFN-32 ...........................................................................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 31-Jan-2014 (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided.
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PACKAGE MATERIALS INFORMATION www.ti.com 11-Feb-2014 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing LM25119PSQ/NOPB WQFN RTV 32 LM25119PSQE/NOPB WQFN RTV LM25119PSQX/NOPB WQFN RTV LM25119QPSQ/NOPB WQFN RTV SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 1000 178.0 12.4 5.3 5.3 1.3 8.0 12.0 Q1 32 250 178.0 12.4 5.3 5.3 1.3 8.0 12.0 Q1 32 4500 330.0 12.4 5.3 5.3 1.
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PACKAGE MATERIALS INFORMATION www.ti.com 11-Feb-2014 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM25119PSQ/NOPB WQFN RTV 32 1000 213.0 191.0 55.0 LM25119PSQE/NOPB WQFN RTV 32 250 213.0 191.0 55.0 LM25119PSQX/NOPB WQFN RTV 32 4500 367.0 367.0 35.0 LM25119QPSQ/NOPB WQFN RTV 32 1000 213.0 191.0 55.
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MECHANICAL DATA RTV0032A SQA32A (Rev B) www.ti.
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