Datasheet

LM25117

LM25117-Q1

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SNVS714E –APRIL 2011–REVISED MARCH 2013

PIN DESCRIPTIONS (continued)

HTSSOP WQFN Name Description

Pin Pin

8 8 FB Feedback. Inverting input of the internal error amplifier. A resistor divider from the output to this pin sets

the output voltage level. The regulation threshold at the FB pin is 0.8V.

9 9 COMP Output of the internal error amplifier. The loop compensation network should be connected between this

pin and the FB pin.

10 10 CM Current monitor output. Average of the sensed inductor current is provided. Monitor directly between CM

and AGND. CM should be left floating when the pin is not used.

11 11 RAMP PWM ramp signal. An external resistor and capacitor connected between the SW pin, the RAMP pin and

the AGND pin sets the PWM ramp slope. Proper selection of component values produces a RAMP

signal that emulates the AC component of the inductor with a slope proportional to input supply voltage.

12 12 CS Current sense amplifier input. Connect to the high-side of the current sense resistor.

13 13 CSG Kelvin ground connection to the current sense resistor. Connect directly to the low-side of the current

sense resistor.

14 14 PGND Power ground return pin for low-side NMOS gate driver. Connect directly to the low-side of the current

sense resistor.

15 15 LO Low-side NMOS gate drive output. Connect to the gate of the low-side synchronous NMOS transistor

through a short, low inductance path.

16 16 VCC Bias supply pin. Locally decouple to PGND using a low ESR/ESL capacitor located as close to controller

as possible.

17 18 SW Switching node of the buck regulator. Connect to the bootstrap capacitor, the source terminal of the

high-side NMOS transistor and the drain terminal of the low-side NMOS through a short, low inductance

path.

18 19 HO High-side NMOS gate drive output. Connect to the gate of the high-side NMOS transistor through a

short, low inductance path.

19 20 HB High-side driver supply for the bootstrap gate drive. Connect to the cathode of the external bootstrap

diode and to the bootstrap capacitor. The bootstrap capacitor supplies current to charge the high-side

NMOS gate and should be placed as close to controller as possible.

20 22 VIN Supply voltage input source for the VCC regulator.

EP EP EP Exposed pad of the package. Electrically isolated. Should be soldered to the ground plane to reduce

thermal resistance.

6 NC No electrical contact.

17 NC No electrical contact.

21 NC No electrical contact.

23 NC No electrical contact.

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

Product Folder Links: LM25117 LM25117-Q1