Datasheet

P
SW
= 0.5 x V
IN
x I
OUT
x (t
R
+ t
F
) x f
SW
[W]
P
GC
= n x V
VCC
x Q
g
x f
SW
[W]
P
DC (Low-Side)
= (1 ± D) x (I
OUT
2
x R
DS(ON)
x 1.3)
[W]
P
DC (High-Side)
= D x (I
OUT
2
x R
DS(ON)
x 1.3)
[W]
1.25V x 50 k:
5.7V - 1.25V
R
UV1
=
= 14.0 k:
1V
20 µA
R
UV2
=
= 50 k:
LM25117
LM25117-Q1
www.ti.com SNVS714E –APRIL 2011–REVISED MARCH 2013
UVLO DIVIDER R
UV2
, R
UV1
AND C
FT
The desired startup voltage and the hysteresis are set by the voltage divider R
UV1
and R
UV2
. Capacitor C
FT
provides filtering for the divider. For this design, the startup voltage was set to 5.7V, 0.3V below V
IN(MIN)
. V
HYS
was set to 1V. The value of R
UV1
, R
UV2
can be calculated from Equation 1 and Equation 2 as follows:
(36)
(37)
The standard value of 50kΩ was selected for R
UV2
. R
UV1
was selected to be 14kΩ. A value of 100pF was chosen
for C
FT
.
VCC DISABLE AND EXTERNAL VCC SUPPLY
In this example, VCCDIS is left floating to enable the internal VCC regulator.
POWER SWITCHES Q
H
and Q
L
Selection of the power NMOS devices is governed by the same trade-offs as switching frequency. Breaking
down the losses in the high-side and low-side NMOS devices is one way to compare the relative efficiencies of
different devices. Losses in the power NMOS devices can be broken down into conduction loss, gate charging
loss, and switching loss.
Conduction loss P
DC
is approximately:
(38)
(39)
Where D is the duty cycle and the factor of 1.3 accounts for the increase in the NMOS device on-resistance due
to heating. Alternatively, the factor of 1.3 can be eliminated and the high temperature on-resistance of the NMOS
device can be estimated using the R
DS(ON)
vs Temperature curves in the MOSFET datasheet.
Gate charging loss (P
GC
) results from the current driving the gate capacitance of the power NMOS devices and is
approximated as:
(40)
Qg refers to the total gate charge of an individual NMOS device, and ‘n’ is the number of NMOS devices. Gate
charge loss differs from conduction and switching losses in that the actual dissipation occurs in the controller IC.
Switching loss (P
SW
) occurs during the brief transition period as the high-side NMOS device turns on and off.
During the transition period both current and voltage are present in the channel of the NMOS device. The
switching loss can be approximated as:
(41)
t
R
and t
F
are the rise and fall times of the high-side NMOS device. The rise and fall times are usually mentioned
in the MOSFET datasheet or can be empirically observed with an oscilloscope. Switching loss is calculated for
the high-side NMOS device only. Switching loss in the low-side NMOS device is negligible because the body
diode of the low-side NMOS device turns on before and after the low-side NMOS device switches. For this
example, the maximum drain-to-source voltage applied to either NMOS device is 36V. The selected NMOS
devices must be able to withstand 36V plus any ringing from drain to source and must be able to handle at least
the VCC voltage plus any ringing from gate to source.
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