Datasheet

PGND
UVLO
AGND
DEMB
RES
SS
RT
FB
COMP
CM
1
6
2
3
4
5
8 9
20
14
15
19
18
17
16
13
1211
VIN
LO
HB
HO
SW
VCC
CSG
CS
RAMP
21222324
VCCDIS
7 10
NC
NC
NC
NC
EP
UVLO
AGND
DEMB
RES
SS
RT
FB
COMP
CM
VIN
PGND
LO
HB
HO
SW
VCC
CSG
CS
RAMP
1
6
2
3
4
5
8
9
20
14
15
19
18
17
16
13
12
11
EP
VCCDIS
10
7
LM25117
LM25117-Q1
SNVS714E –APRIL 2011–REVISED MARCH 2013 www.ti.com
Connection Diagram
Figure 1. Top View Figure 2. Top View
20-Lead HTSSOP WQFN-24 (4mmx4mm)
PIN DESCRIPTIONS
HTSSOP WQFN Name Description
Pin Pin
1 24 UVLO Under-voltage lockout programming pin. If the UVLO pin voltage is below 0.4V, the regulator is in the
shutdown mode with all functions disabled. If the UVLO pin voltage is greater than 0.4V and less than
1.25V, the regulator is in standby mode with the VCC regulator operational, the SS pin grounded, and no
switching at the HO and LO outputs. If the UVLO pin voltage is above 1.25V, the SS pin is allowed to
ramp and pulse width modulated gate drive signals are delivered to the HO and LO pins. A 20μA current
source is enabled when UVLO exceeds 1.25V and flows through the external UVLO resistors to provide
hysteresis.
2 1 DEMB Optional logic input that enables diode emulation when in the low state. In diode emulation mode, the
low-side NMOS is latched off for the remainder of the PWM cycle after detecting reverse current flow
(current flow from output to ground through the low-side NMOS). When DEMB is high, diode emulation
is disabled allowing current to flow in either direction through the low-side NMOS. A 50kΩ pull-down
resistor internal to the LM25117 holds DEMB pin low and enables diode emulation if the pin is left
floating.
3 2 RES The restart timer pin that configures the hiccup mode current limiting. A capacitor on the RES pin
determines the time the controller remains off before automatically restarting. The hiccup mode
commences when the controller experiences 256 consecutive PWM cycles of cycle-by-cycle current
limiting. After this occurs, an 10μA current source charges the RES pin capacitor to the 1.25V threshold
and restarts LM25117.
4 3 SS An external capacitor and an internal 10μA current source set the ramp rate of the error amplifier
reference during soft-start. The SS pin is held low when VCC< 4V, UVLO < 1.25V or during thermal
shutdown.
5 4 RT The internal oscillator is programmed with a single resistor between RT and the AGND. The
recommended maximum oscillator frequency is 750kHz. The internal oscillator can be synchronized to
an external clock by coupling a positive pulse into the RT pin through a small coupling capacitor.
6 5 AGND Analog ground. Return for the internal 0.8V voltage reference and analog circuits.
7 7 VCCDIS Optional input that disables the internal VCC regulator. If VCCDIS>1.25V, the internal VCC regulator is
disabled. VCCDIS has an internal 500kΩ pull-down resistor to enable the VCC regulator when the pin is
left floating. The internal 500kΩ pull-down resistor can be overridden by pulling VCCDIS above 1.25V
with a resistor divider connected to an external bias supply.
2 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated
Product Folder Links: LM25117 LM25117-Q1