Datasheet
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CM _ AVE PEAK VALLEY S S
V I I R A V= + ´ ´
CM
A
M
= 2
40 k:
R
CM
C
CM
Current Monitor
Amplifier
Current Sense
Amplifier Output
LM25117
CONDITIONER
LM25117
LM25117-Q1
www.ti.com
SNVS714E –APRIL 2011–REVISED MARCH 2013
HO and LO Drivers
The LM25117 contains high current NMOS drivers and an associated high-side level shifter to drive the external
high-side NMOS device. This high-side gate driver works in conjunction with an external diode D
HB
, and
bootstrap capacitor C
HB
. A 0.1μF or larger ceramic capacitor, connected with short traces between the HB and
SW pin, is recommended. During the off-time of the high-side NMOS driver, the SW pin voltage is approximately
0V and the C
HB
is charged from VCC through the D
HB
. When operating with a high PWM duty cycle, the high-
side NMOS device is forced off each cycle for 320ns to ensure that C
HB
is recharged.
The LO and HO outputs are controlled with an adaptive dead-time methodology which insures that both outputs
are never enabled at the same time. When the controller commands HO to be enabled, the adaptive dead-time
logic first disables LO and waits for the LO voltage to drop. HO is then enabled after a small delay (LO Fall to HO
Rise Delay). Similarly, the LO turn-on is delayed until the HO voltage has discharged. LO is then enabled after a
small delay (HO Fall to LO Rise Delay). This technique insures adequate dead-time for any size NMOS device,
especially when VCC is supplied by a higher external voltage source. The adaptive dead-time circuitry monitors
the voltages of HO and LO outputs and insures the dead-time between the HO and LO outputs. Adding a gate
resister, R
GH
or R
GL
, may decrease the effective dead-time.
Care should be exercised in selecting an output NMOS device with the appropriate threshold voltage, especially
if VCC is supplied by an external bias supply voltage below the VCC regulation level. During startup at low input
voltages, the low-side NMOS device gate plateau voltage should be lower than the VCC under-voltage lockout
threshold. Otherwise, there may be insufficient VCC voltage to completely enhance the NMOS device as the
VCC under-voltage lockout is released during startup. If the high-side NMOS drive voltage is lower than the high-
side NMOS device gate plateau voltage during startup, the regulator may not start or it may hang up momentarily
in a high power dissipation state. This condition can be addressed by selecting an NMOS device with a lower
threshold voltage. This situation can be avoided if the minimum input voltage programmed by the UVLO resistor
is above the VCC regulation level.
Current Monitor
The LM25117 provides average output current information, enabling various applications requiring monitoring or
control of the output current.
Figure 30. Current Monitor
The average of CM output can be calculated by:
(14)
The current monitor output is only valid in continuous conduction operation. The current monitor has a limited
bandwidth of approximately one tenth of f
SW
. Adding an R-C filter, R
CM
and C
CM
, on the output of current monitor
with the cut off frequency below one tenth of f
SW
is recommended to attenuate sampling noise.
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Product Folder Links: LM25117 LM25117-Q1