Datasheet

5.2 x 10
9
R
T
=
- 948 [5]
f
SW
1.25V x R
UV2
R
UV1
=
V
IN(STARTUP)
- 1.25V
[5]
V
HYS
R
UV2
=
20 µA
[5]
LM25117
V
IN
UVLO
Shutdown
Threshold
SHUTDOWN
UVLO
Threshold
UVLO Hysteresis
Current
UVLO
+
-
+
-
C
FT
R
UV2
R
UV1
STANDBY
LM25117
LM25117-Q1
www.ti.com SNVS714E –APRIL 2011–REVISED MARCH 2013
Figure 22. UVLO Configuration
The UVLO pin should not be left floating. An external UVLO set-point voltage divider from the VIN to AGND is
used to set the minimum input operating voltage of the regulator. The divider must be designed such that the
voltage at the UVLO pin is greater than 1.25V and never exceeds 15V when the input voltage is in the desired
operating range. If necessary, the UVLO pin can be clamped with a Zener diode.
UVLO hysteresis is accomplished with an internal 20μA current source that is switched on or off into the
impedance of the UVLO set-point divider. When the UVLO pin voltage exceeds the 1.25V threshold, the current
source is enabled to quickly raise the voltage at the UVLO pin. When the UVLO pin voltage falls below the 1.25V
threshold, the current source is disabled causing the voltage at the UVLO pin to quickly fall. The use of a C
FT
capacitor in parallel with R
UV1
helps to minimize switching noise injection into UVLO pin, but it may slow down
the falling speed of the UVLO pin when the 20μA current source is disabled. The recommended range for C
FT
is
10pF to 220pF.
The values of R
UV1
and R
UV2
can be determined from the following equations:
(1)
(2)
Where V
HYS
is the desired UVLO hysteresis and V
IN(STARTUP)
is the desired startup voltage of the regulator during
turn-on.
Oscillator and Sync Capability
The LM25117 switching frequency is programmed by a single external resistor connected between the RT pin
and the AGND pin. The resistor should be located very close to the device and connected directly to the RT and
AGND pins. To set a desired switching frequency (f
SW
), the resistor value can be calculated from the following
equation:
(3)
The RT pin can be used to synchronize the internal oscillator to an external clock. The internal oscillator can be
synchronized by AC coupling a positive edge into the RT pin. The voltage at the RT pin is nominally 1.25V and
the voltage at the RT pin must exceed the RT Sync Positive Threshold to trip the internal synchronization pulse
detector. A 5V amplitude pulse signal coupled through 100pF capacitor is a good starting point. The frequency of
the external synchronization pulse is recommended to be within +/-10% of the frequency programmed by the RT
resistor but will operate to +100/-40% of the programmed frequency. Care should be taken to make sure that the
RT pin voltage does not go below -0.3V at the falling edge of the external pulse. This may limit the duty cycle of
external synchronization pulse.
The R
T
resistor is always required, whether the oscillator is free running or externally synchronized.
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