Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsPMICsPMIC - voltage regulators - DC DC switch controllers HTSSOP 20

OUT

SSRESRT

COMP

RAMP

PGND

CSG

VCCVIN

AGND

UVLO

VCCDIS

DEMB

OUT

LM25117

LM25117-Q1

www.ti.com

SNVS714E –APRIL 2011–REVISED MARCH 2013

Wide Input Range Synchronous Buck Controller with Analog Current Monitor

Check for Samples: LM25117, LM25117-Q1

FEATURES

DESCRIPTION

The LM25117 is a synchronous buck controller

• LM25117Q is an Automotive Grade Product

intended for step-down regulator applications from a

that is AEC-Q100 Grade 1 Qualified (-40°C to

high voltage or widely varying input supply. The

+125°C Operating Junction Temperature)

control method is based upon current mode control

• Emulated Peak Current Mode Control

utilizing an emulated current ramp. Current mode

control provides inherent line feed-forward, cycle-by-

• Wide Operating Range from 4.5V to 42V

cycle current limiting and ease of loop compensation.

• Robust 3.3A Peak Gate Drives

The use of an emulated control ramp reduces noise

• Adaptive Dead-time Output Driver Control

sensitivity of the pulse-width modulation circuit,

• Free-run or Synchronizable Clock up to

allowing reliable control of very small duty cycles

necessary in high input voltage applications.

750kHz

• Optional Diode Emulation Mode

The operating frequency is programmable from 50

kHz to 750 kHz. The LM25117 drives external high-

• Programmable Output from 0.8V

side and low-side NMOS power switches with

• Precision 1.5% Voltage Reference

adaptive dead-time control. A user-selectable diode

• Analog Current Monitor

emulation mode enables discontinuous mode

operation for improved efficiency at light load

• Programmable Current Limit

conditions. A high voltage bias regulator that allows

• Hiccup Mode Over Current Protection

external bias supply further improves efficiency. The

• Programmable Soft-start and Tracking

LM25117’s unique analog telemetry feature provides

• Programmable Line Under-voltage Lockout average output current information. Additional

features include thermal shutdown, frequency

• Programmable Switch-over to External Bias

synchronization, hiccup mode current limit and

Supply

adjustable line under-voltage lockout.

• Thermal Shutdown

• Available Package: HTSSOP-20 (Thermally

Enhanced), WQFN-24 (4mm×4mm)

Typical Application

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (43 pages)

PAGE 1
LM25117 LM25117-Q1 www.ti.com SNVS714E – APRIL 2011 – REVISED MARCH 2013 Wide Input Range Synchronous Buck Controller with Analog Current Monitor Check for Samples: LM25117, LM25117-Q1 FEATURES DESCRIPTION • The LM25117 is a synchronous buck controller intended for step-down regulator applications from a high voltage or widely varying input supply. The control method is based upon current mode control utilizing an emulated current ramp.
PAGE 2
LM25117 LM25117-Q1 SNVS714E – APRIL 2011 – REVISED MARCH 2013 www.ti.com 2 19 HB RES 3 18 HO SS 4 17 SW RT 5 16 VCC 15 LO HO DEMB HB VIN NC 20 VIN 1 NC UVLO UVLO Connection Diagram 24 23 22 21 20 19 DEMB 1 18 SW RES 2 17 NC SS 3 16 VCC EP PGND FB 8 13 CSG COMP 9 12 CS CM 10 11 RAMP RT 4 15 LO AGND 5 14 PGND NC 6 13 CSG VCCDIS 7 Figure 1.
PAGE 3
LM25117 LM25117-Q1 www.ti.com SNVS714E – APRIL 2011 – REVISED MARCH 2013 PIN DESCRIPTIONS (continued) HTSSOP Pin WQFN Pin Name Description 8 8 FB Feedback. Inverting input of the internal error amplifier. A resistor divider from the output to this pin sets the output voltage level. The regulation threshold at the FB pin is 0.8V. 9 9 COMP Output of the internal error amplifier. The loop compensation network should be connected between this pin and the FB pin. 10 10 CM Current monitor output.
PAGE 4
LM25117 LM25117-Q1 SNVS714E – APRIL 2011 – REVISED MARCH 2013 www.ti.com Absolute Maximum Ratings (1) VIN to AGND -0.3 to 45V SW to AGND -3.0 to 45V HB to SW -0.3 to 15V VCC to AGND (2) -0.3 to 15V HO to SW -0.3 to HB+0.3V LO to AGND -0.3 to VCC+0.3V FB, DEMB, RES, VCCDIS, UVLO to AGND CM, COMP to AGND -0.3 to 15V (3) -0.3 to 7V SS, RAMP, RT to AGND -0.3 to 7V CS, CSG, PGND, to AGND -0.3 to 0.
PAGE 5
LM25117 LM25117-Q1 www.ti.com SNVS714E – APRIL 2011 – REVISED MARCH 2013 Electrical Characteristics Limits in standard type are for TJ = 25°C only; limits in boldface type apply over the junction temperature range of -40°C to +125°C. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise specified, the following conditions apply: VVIN = 24V, VVCCDIS = 0V, RT = 25kΩ, no load on LO & HO.
PAGE 6
LM25117 LM25117-Q1 SNVS714E – APRIL 2011 – REVISED MARCH 2013 www.ti.com Electrical Characteristics (continued) Limits in standard type are for TJ = 25°C only; limits in boldface type apply over the junction temperature range of -40°C to +125°C. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise specified, the following conditions apply: VVIN = 24V, VVCCDIS = 0V, RT = 25kΩ, no load on LO & HO.
PAGE 7
LM25117 LM25117-Q1 www.ti.com SNVS714E – APRIL 2011 – REVISED MARCH 2013 Typical Performance Characteristics HO Peak Driver Current vsOutput Voltage LO Peak Driver Current vs Output Voltage Figure 3. Figure 4. Driver Dead Time vs VVCC Driver Dead Time vs Temperature Figure 5. Figure 6. Forced HO Off-time vs Temperature Switching Frequency vs RT Figure 7. Figure 8.
PAGE 8
LM25117 LM25117-Q1 SNVS714E – APRIL 2011 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) 8 VVCC vs IVCC VVCC vs VVIN Figure 9. Figure 10. VCS(TH) vs Temperature VREF vs Temperature Figure 11. Figure 12. VVCC vs Temperature Error Amp Gain and Phase vs Frequency Figure 13. Figure 14.
PAGE 9
LM25117 LM25117-Q1 www.ti.com SNVS714E – APRIL 2011 – REVISED MARCH 2013 Typical Performance Characteristics (continued) VCM vs IOUT VCM vs VCSG-CS Figure 15. Figure 16.
PAGE 10
Submit Documentation Feedback SYNC CSYNC CSS Product Folder Links: LM25117 LM25117-Q1 CRES CHF RT RUV1 RUV2 RCOMP CCOMP CFT CIN REF RES RES Current COMP FB SS RT + + ERR + AMP - + + - RESTART TIMER - 1.
PAGE 11
LM25117 LM25117-Q1 www.ti.com SNVS714E – APRIL 2011 – REVISED MARCH 2013 FUNCTIONAL DESCRIPTION The LM25117 high voltage switching controller features all of the functions necessary to implement an efficient high voltage buck regulator that operates over a very wide input voltage range. This easy to use controller integrates high-side and low-side NMOS drivers. The regulator control method is based upon peak current mode control utilizing an emulated current ramp.
PAGE 12
LM25117 LM25117-Q1 SNVS714E – APRIL 2011 – REVISED MARCH 2013 www.ti.com VOUT VCC LM25117 VCCDIS resistor divider is required when external VCC supplying voltage is smaller than 8.5V VCCDIS Figure 19. External VCC Supply for 5V< VOUT<14.5V For VOUT < 5V, a bias winding on the output inductor can be added to generate the external VCC supply voltage. VCC LM25117 VCCDIS VOUT SW VCCDIS resistor divider is required when external VCC supplying voltage is smaller than 8.5V Figure 20.
PAGE 13
LM25117 LM25117-Q1 www.ti.com SNVS714E – APRIL 2011 – REVISED MARCH 2013 UVLO Hysteresis Current VIN UVLO Threshold RUV2 UVLO CFT RUV1 LM25117 UVLO Shutdown Threshold + + STANDBY SHUTDOWN Figure 22. UVLO Configuration The UVLO pin should not be left floating. An external UVLO set-point voltage divider from the VIN to AGND is used to set the minimum input operating voltage of the regulator. The divider must be designed such that the voltage at the UVLO pin is greater than 1.
PAGE 14
LM25117 LM25117-Q1 SNVS714E – APRIL 2011 – REVISED MARCH 2013 www.ti.com Ramp Generator and Emulated Current Sense The ramp signal used in the pulse width modulator for traditional current mode control is typically derived directly from the high-side switch current. This switch current corresponds to the positive slope portion of the inductor current.
PAGE 15
LM25117 LM25117-Q1 www.ti.com SNVS714E – APRIL 2011 – REVISED MARCH 2013 The positive slope inductor current ramp is emulated by CRAMP connected between RAMP and AGND and RRAMP connected between SW and RAMP. RRAMP should not be connected to VIN directly because the RAMP pin absolute maximum voltage rating could be exceeded under high input voltage conditions. CRAMP is discharged by an internal switch during the off-time and must be fully discharged during the minimum off-time.
PAGE 16
LM25117 LM25117-Q1 SNVS714E – APRIL 2011 – REVISED MARCH 2013 www.ti.com Diode Emulation A fully synchronous buck regulator implemented with a freewheeling NMOS rather than a diode has the capability to sink current from the output in certain conditions such as light load, over-voltage or pre-bias startup. The LM25117 provides a diode emulation feature that can be enabled to prevent reverse current flow in the lowside NMOS device.
PAGE 17
LM25117 LM25117-Q1 www.ti.com SNVS714E – APRIL 2011 – REVISED MARCH 2013 IPP IOUT T= 1 fSW 0 Figure 26. Inductor Current During an output short condition, the worst case peak inductor current is limited to: VIN(MAX) x tON(MIN) VCS(TH) ILIM_PK = RS + [A] LO (12) Where tON(MIN) is the minimum HO on-time. In most of cases, especially if the output voltage is relatively high, it is recommended that a soft-saturating inductor such as a powder core device is used.
PAGE 18
LM25117 LM25117-Q1 SNVS714E – APRIL 2011 – REVISED MARCH 2013 www.ti.com Current Limit Detected 1.25V RES Threshold IRES = 10 µA RES 0V ISS = 10 µA SS 0.8V REF HO LO Current Limit persists during 256 consecutive cycles tRES tSS Figure 27. Hiccup Mode Current Limit Timing Diagram LM25117 STANDBY RES Current RESTART TIMER HICCUP RES CRES HICCUP MODE FAULT TIMER 256 CYCLES Current Limit Comparator + Figure 28.
PAGE 19
LM25117 LM25117-Q1 www.ti.com SNVS714E – APRIL 2011 – REVISED MARCH 2013 HO and LO Drivers The LM25117 contains high current NMOS drivers and an associated high-side level shifter to drive the external high-side NMOS device. This high-side gate driver works in conjunction with an external diode DHB, and bootstrap capacitor CHB. A 0.1μF or larger ceramic capacitor, connected with short traces between the HB and SW pin, is recommended.
PAGE 20
LM25117 LM25117-Q1 SNVS714E – APRIL 2011 – REVISED MARCH 2013 www.ti.com Maximum Duty Cycle When operating with a high PWM duty cycle, the high-side NMOS device is forced off each cycle for 320ns to ensure that CHB is recharged and to allow time to sample and hold the current in the low-side NMOS FET. This forced off-time limits the maximum duty cycle of the controller.
PAGE 21
LM25117 LM25117-Q1 www.ti.com SNVS714E – APRIL 2011 – REVISED MARCH 2013 APPLICATION INFORMATION FEEDBACK COMPENSATION Open loop response of the regulator is defined as the product of modulator transfer function and feedback transfer function. When plotted on a dB scale, the open loop gain is shown as the sum of modulator gain and feedback gain.
PAGE 22
LM25117 LM25117-Q1 SNVS714E – APRIL 2011 – REVISED MARCH 2013 www.ti.com For higher crossover frequency, RCOMP can be increased, while proportionally decreasing CCOMP. Conversely, decreasing RCOMP while proportionally increasing CCOMP, results in lower bandwidth while keeping the same zero frequency in the feedback transfer function. The sampled gain inductor pole is inversely proportional to the K factor, which is defined as: fSW Zp_HF = K - 0.
PAGE 23
LM25117 LM25117-Q1 www.ti.com SNVS714E – APRIL 2011 – REVISED MARCH 2013 Figure 33. dl1/dl0 vs K Factor The minimum value of K is 0.5. When K<0.5, the amplitude of dI1 is greater than the amplitude of dI0 and any initial perturbation results in sub-harmonic oscillation. If K=1, any initial perturbation will be removed in one switching cycle. This is known as one-cycle damping. When -1
PAGE 24
LM25117 LM25117-Q1 SNVS714E – APRIL 2011 – REVISED MARCH 2013 www.ti.com PC BOARD LAYOUT RECOMMENDATION In a buck regulator the primary switching loop consists of the input capacitor, NMOS power switches and current sense resistor. Minimizing the area of this loop reduces the stray inductance and minimizes noise and possible erratic operation.
PAGE 25
LM25117 LM25117-Q1 www.ti.com SNVS714E – APRIL 2011 – REVISED MARCH 2013 Table 1.
PAGE 26
LM25117 LM25117-Q1 SNVS714E – APRIL 2011 – REVISED MARCH 2013 www.ti.com Table 1.
PAGE 27
LM25117 LM25117-Q1 www.ti.com SNVS714E – APRIL 2011 – REVISED MARCH 2013 DESIGN EXAMPLE OPERATING CONDITIONS • • • • • • • Output Voltage VOUT = 3.3V Full Load Current IOUT = 9A Minimum Input Voltage VIN(MIN) = 6V Maximum Input Voltage VIN(MAX) = 36V Switching Frequency fSW = 230kHz Diode Emulation Yes External VCC Supply No TIMING RESISTOR RT Generally, higher frequency applications are smaller but have higher losses.
PAGE 28
LM25117 LM25117-Q1 SNVS714E – APRIL 2011 – REVISED MARCH 2013 www.ti.com CURRENT SENSE RESISTOR RS The performance of the converter will vary depending on the K value. For this example, K=1 was chosen to control sub-harmonic oscillation and achieve one-cycle damping. The maximum output current capability (IOUT(MAX)) should be 20~50% higher than the required output current, to account for tolerances and ripple current. For this example, 150% of 9A was chosen.
PAGE 29
LM25117 LM25117-Q1 www.ti.com SNVS714E – APRIL 2011 – REVISED MARCH 2013 UVLO DIVIDER RUV2, RUV1 AND CFT The desired startup voltage and the hysteresis are set by the voltage divider RUV1 and RUV2. Capacitor CFT provides filtering for the divider. For this design, the startup voltage was set to 5.7V, 0.3V below VIN(MIN). VHYS was set to 1V. The value of RUV1, RUV2 can be calculated from Equation 1 and Equation 2 as follows: 1V = 50 k: RUV2 = 20 µA (36) RUV1 = 1.25V x 50 k: = 14.0 k: 5.7V - 1.
PAGE 30
LM25117 LM25117-Q1 SNVS714E – APRIL 2011 – REVISED MARCH 2013 www.ti.com SNUBBER COMPONENTS RSNB AND CSNB A resistor-capacitor snubber network across the low-side NMOS device reduces ringing and spikes at the switching node. Excessive ringing and spikes can cause erratic operation and can couple noise to the output voltage. Selecting the values for the snubber is best accomplished through empirical methods. First, make sure the lead lengths for the snubber connections are very short.
PAGE 31
LM25117 LM25117-Q1 www.ti.com 'VIN = SNVS714E – APRIL 2011 – REVISED MARCH 2013 IOUT 4 x fSW x CIN [V] (45) 'VIN = 9A = 0.63V 4 x 230 kHz x 2.2 PH x 7 (46) Capacitors connected in parallel should be evaluated for RMS current rating. The current will split between the input capacitors based on the relative impedance of the capacitors at the switching frequency. VIN FILTER RVIN, CVIN An R-C filter (RVIN, CVIN) on VIN is optional.
PAGE 32
LM25117 LM25117-Q1 SNVS714E – APRIL 2011 – REVISED MARCH 2013 www.ti.com RCOMP = 2S x 8 m: x 10 x 724 µF x 3.24 k: x 23 kHz = 27.1 k: (52) The standard value of 27.4kΩ was selected for RCOMP STEP3: Determine CCOMP to cancel load pole Knowing RCOMP, CCOMP is calculated as follows: RLOAD x COUT [F] CCOMP = RCOMP CCOMP = 3.3V 9A (53) x 724 µF 27.
PAGE 33
LM25117 LM25117-Q1 www.ti.com SNVS714E – APRIL 2011 – REVISED MARCH 2013 Application Circuit Figure 35. 3.
PAGE 34
LM25117 LM25117-Q1 SNVS714E – APRIL 2011 – REVISED MARCH 2013 www.ti.com Example of Constant Current Regulator The LM25117 can be configured as a constant current regulator by using the current monitor feature (CM) as the feedback input. A voltage divider at the VCCDIS pin from VOUT to AGND can be used to protect against output over-voltage. When the VCCDIS pin voltage is greater than the VCCDIS threshold, the controller disables the VCC regulator and the VCC pin voltage decays.
PAGE 35
LM25117 LM25117-Q1 www.ti.com SNVS714E – APRIL 2011 – REVISED MARCH 2013 VIN Current Control (CC) 100 k: VCC CIN UVLO VIN SW 10 k: 100: 15 k: RES DEMB VCC LM25117 100 k: PNP CVCC DHB HB RAMP CHB 1 nF 1500 pF HO 100 k: CM QH 68 PH VOUT CV Mode : 5V CC Mode: 2A SW LMV431 200 k: LO VCCDIS QL 80 PF CS 47 m: VOUT 3.24 k: CSG 34.8 k: 0.1 PF COMP FB RT SS AGND PGND 619: 22.1 k: 0.33 PF x2 Voltage Control (CV) Figure 37.
PAGE 36
LM25117 LM25117-Q1 SNVS714E – APRIL 2011 – REVISED MARCH 2013 www.ti.com REVISION HISTORY Changes from Revision D (March 2013) to Revision E • 36 Page Changed layout of National Data Sheet to TI format ..........................................................................................................
PAGE 37
PACKAGE OPTION ADDENDUM www.ti.
PAGE 38
PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
PAGE 39
PACKAGE MATERIALS INFORMATION www.ti.com 11-Oct-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) LM25117PMHE/NOPB HTSSOP PWP 20 250 178.0 16.4 LM25117PMHX/NOPB HTSSOP PWP 20 2500 330.0 LM25117PSQ/NOPB WQFN RTW 24 1000 178.
PAGE 40
PACKAGE MATERIALS INFORMATION www.ti.com 11-Oct-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM25117PMHE/NOPB HTSSOP PWP LM25117PMHX/NOPB HTSSOP PWP 20 250 213.0 191.0 55.0 20 2500 367.0 367.0 38.0 LM25117PSQ/NOPB WQFN RTW 24 1000 210.0 185.0 35.0 LM25117PSQE/NOPB WQFN RTW 24 250 210.0 185.0 35.0 LM25117PSQX/NOPB WQFN RTW 24 4500 367.0 367.0 35.
PAGE 41
MECHANICAL DATA PWP0020A MXA20A (Rev C) www.ti.
PAGE 42
MECHANICAL DATA RTW0024A SQA24A (Rev B) www.ti.
PAGE 43
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.