Datasheet
5 PA
t
OFF
= C
FT
x
1.215V
t
OFF
= -
R
UV1
x R
UV2
R
UV1
+ R
UV2
x C
FT
x ln
1 -
1.215 x (R
UV1
+ R
UV2
)
V
IN
x R
UV1
R
UV1
= 1.215 x
R
UV2
V
IN(MIN)
+ (5 PA x R
UV2
) - 1.215
LM25116
SNVS509D –APRIL 2007–REVISED FEBRUARY 2013
www.ti.com
2. With an appropriate value for R
UV2
, R
UV1
can be selected using Equation 25.
where
• V
IN(MIN)
is the desired shutdown voltage. (25)
3. Capacitor C
FT
provides filtering for the divider and determines the off-time of the “hiccup” duty cycle during
current limit. When C
FT
is used in conjunction with the voltage divider, a diode across the top resistor should
be used to discharge C
FT
in the event of an input under-voltage condition.
(26)
If under-voltage shutdown is not required, R
UV1
and R
UV2
can be eliminated and the off-time becomes:
(27)
The voltage at the UVLO pin should never exceed 16V when using an external set-point divider. It may be
necessary to clamp the UVLO pin at high input voltages. For the design example, R
UV2
= 102 kΩ and R
UV1
= 21
kΩ for a shut-down voltage of 6.6V. If sustained short circuit protection is required, C
FT
≥ 1 µF will limit the short
circuit power dissipation. D2 may be installed when using C
FT
with R
UV1
and R
UV2
.
MOSFETs
Selection of the power MOSFETs is governed by the same tradeoffs as switching frequency. Breaking down the
losses in the high-side and low-side MOSFETs is one way to determine relative efficiencies between different
devices. When using discrete SO-8 MOSFETs the LM25116 is most efficient for output currents of 2A to 10A.
Losses in the power MOSFETs can be broken down into conduction loss, gate charging loss, and switching loss.
Conduction, or I
2
R loss P
DC
, is approximately:
P
DC(HO-MOSFET)
= D x (I
O
2
x R
DS(ON)
x 1.3) (28)
P
DC(LO-MOSFET)
= (1 - D) x (I
O
2
x R
DS(ON)
x 1.3)
where
• D is the duty cycle. The factor 1.3 accounts for the increase in MOSFET on-resistance due to heating.
Alternatively, the factor of 1.3 can be ignored and the on-resistance of the MOSFET can be estimated using
the R
DS(ON)
vs Temperature curves in the MOSFET datasheet. Gate charging loss, P
GC
, results from the
current driving the gate capacitance of the power MOSFETs and is approximated as: (29)
P
GC
= n x VCC x Q
g
x f
SW
(30)
Q
g
refers to the total gate charge of an individual MOSFET, and ‘n’ is the number of MOSFETs. If different types
of MOSFETs are used, the ‘n’ term can be ignored and their gate charges summed to form a cumulative Q
g
.
Gate charge loss differs from conduction and switching losses in that the actual dissipation occurs in the
LM25116 and not in the MOSFET itself. Further loss in the LM25116 is incurred as the gate driving current is
supplied by the internal linear regulator. The gate drive current supplied by the VCC regulator is calculated as:
I
GC
= (Q
gh
+ Q
gl
) x f
SW
where
• Q
gh
+ Q
gl
represent the gate charge of the HO and LO MOSFETs at VGS = VCC. To ensure start-up, I
GC
should be less than the VCC current limit rating of 15 mA minimum when powered by the internal 7.4V
regulator. Failure to observe this rating may result in excessive MOSFET heating and potential damage. The
I
GC
run current may exceed 15 mA when VCC is powered by VCCX. (31)
Switching loss occurs during the brief transition period as the MOSFET turns on and off. During the transition
period both current and voltage are present in the channel of the MOSFET. The switching loss can be
approximated as:
P
SW
= 0.5 x V
IN
x I
O
x (t
R
+ t
F
) x f
SW
where
• t
R
and t
F
are the rise and fall times of the MOSFET. Switching loss is calculated for the high-side MOSFET
only. Switching loss in the low-side MOSFET is negligible because the body diode of the low-side MOSFET
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