Datasheet

V
OUT
1.215V
R
FB2
R
FB1
=
- 1
t
SS
x 10 PA
C
SS
=
1.215V
'V
HB
Q
g
C
HB
t
LM25116
www.ti.com SNVS509D –APRIL 2007–REVISED FEBRUARY 2013
When δ = 1, the input filter is critically damped. This may be difficult to achieve with practical component values.
With δ < 0.2, the input filter will exhibit significant ringing. If δ is zero or negative, there is not enough resistance
in the circuit and the input filter will sustain an oscillation. When operating near the minimum input voltage, an
aluminum electrolytic capacitor across C
IN
may be needed to damp the input for a typical bench test setup. Any
parallel capacitor should be evaluated for its RMS current rating. The current will split between the ceramic and
aluminum capacitors based on the relative impedance at the switching frequency.
VCC CAPACITOR
The primary purpose of the VCC capacitor (C
VCC
) is to supply the peak transient currents of the LO driver and
bootstrap diode (D1) as well as provide stability for the VCC regulator. These current peaks can be several
amperes. The recommended value of C
VCC
should be no smaller than 0.47 µF, and should be a good quality, low
ESR, ceramic capacitor located at the pins of the IC to minimize potentially damaging voltage transients caused
by trace inductance. A value of 1 µF was selected for this design.
BOOTSTRAP CAPACITOR
The bootstrap capacitor (C
HB
) between the HB and SW pins supplies the gate current to charge the high-side
MOSFET gate at each cycle’s turn-on as well as supplying the recovery charge for the bootstrap diode (D1).
These current peaks can be several amperes. The recommended value of the bootstrap capacitor is at least 0.1
µF, and should be a good quality, low ESR, ceramic capacitor located at the pins of the IC to minimize potentially
damaging voltage transients caused by trace inductance. The absolute minimum value for the bootstrap
capacitor is calculated as:
where
• Q
g
is the high-side MOSFET gate charge and ΔV
HB
is the tolerable voltage droop on C
HB
, which is typically
less than 5% of VCC. A value of 1 µF was selected for this design. (21)
SOFT START CAPACITOR
The capacitor at the SS pin (C
SS
) determines the soft-start time, which is the time for the reference voltage and
the output voltage to reach the final regulated value. The soft-start time t
SS
should be substantially longer than
the time required to charge C
OUT
to V
OUT
at the maximum output current. To meet this requirement:
t
SS
> V
OUT
x C
OUT
/ (I
CURRENT LIMIT
– I
OUT
) (22)
The value of C
SS
for a given time is determined from:
(23)
For this application, a value of 0.01 µF was chosen for a soft-start time of 1.2 ms.
OUTPUT VOLTAGE DIVIDER
R
FB1
and R
FB2
set the output voltage level, the ratio of these resistors is calculated from:
(24)
R
FB1
is typically 1.21 kΩ for a divider current of 1 mA. The divider current can be reduced to 100 µA with
R
FB1
=12.1 kΩ. For the 5V output design example used here, R
FB1
= 1.21 kΩ and R
FB2
= 3.74 kΩ.
UVLO DIVIDER
A voltage divider and filter can be connected to the UVLO pin to set a minimum operating voltage V
IN(MIN)
for the
regulator. If this feature is required, the following procedure can be used to determine appropriate resistor values
for R
UV2
, R
UV1
and C
FT
.
1. R
UV2
must be large enough such that in the event of a current limit, the internal UVLO switch can pull UVLO
< 200 mV. This can be ensured if:R
UV2
> 500 x V
IN(MAX),
where V
IN(MAX)
is the maximum input voltage and
R
UV2
is in ohms.
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