Datasheet

LM25116
SNVS509D –APRIL 2007–REVISED FEBRUARY 2013 www.ti.com
Components R
COMP
and C
COMP
configure the error amplifier as a type II configuration. The DC gain of the
amplifier is 80 dB which has a pole at low frequency and a zero at f
ZEA
= 1 / (2π x R
COMP
x C
COMP
). The error
amplifier zero cancels the modulator pole leaving a single pole response at the crossover frequency of the
voltage loop. A single pole response at the crossover frequency yields a very stable loop with 90° of phase
margin. For the design example, a target loop bandwidth (crossover frequency) of one-tenth the switching
frequency or 25 kHz was selected. The compensation network zero (f
ZEA
) should be selected at least an order of
magnitude less than the target crossover frequency. This constrains the product of R
COMP
and C
COMP
for a
desired compensation network zero 1 / (2π x R
COMP
x C
COMP
) to be 2.5 kHz. Increasing R
COMP
, while
proportionally decreasing C
COMP
, increases the error amp gain. Conversely, decreasing R
COMP
while
proportionally increasing C
COMP
, decreases the error amp gain. For the design example C
COMP
was selected as
3300 pF and R
COMP
was selected as 18 kΩ. These values configure the compensation network zero at 2.7 kHz.
The error amp gain at frequencies greater than f
ZEA
is: R
COMP
/ R
FB2
, which is approximately 4.8 (13.6 dB).
Figure 37. Error Amplifier Gain and Phase
The overall voltage loop gain can be predicted as the sum (in dB) of the modulator gain and the error amp gain.
Figure 38. Overall Voltage Loop Gain and Phase
24 Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated
Product Folder Links: LM25116