Datasheet

T
restart_delay
=
C
RES
x 1.2V
50 PA
= C
RES
x 24k
R
UV1
= 1.2V x
R
UV2
(V
IN(min)
+ (5 PA x R
UV2
) - 1.2V)
R
FB2
R
FB1
VOUT
1.205V
=
-1
LM25088
LM25088-Q1
SNVS609H –DECEMBER 2008–REVISED MARCH 2013 www.ti.com
OUTPUT VOLTAGE DIVIDER
R
FB1
and R
FB2
set the output voltage level, the ratio of these resistors can be calculated from:
(20)
1.62 kΩ was chosen for R
FB1
in this design which results in a R
FB2
value of 5.11 kΩ. A reasonable guide is to
select the value of R
FB1
value such that the current through the resistor (1.2V/ R
FB1
) is in between 1 mA and 100
µA.
UVLO DIVIDER
A voltage divider can be connected to the EN pin to the set the minimum startup voltage (VIN
(min)
) of the
regulator. If this feature is required, set the value of R
UV2
between 10 kΩ and 100 kΩ and then calculate R
UV1
from:
(21)
In this design, for a VIN
(min)
of 5V, R
UV2
was selected to be 54.9 kΩ resulting in a R
UV1
value of 16.2 kΩ. it is
recommended to install a capacitor parallel to R
UV1
for filtering. If the EN pin is left open, the LM25088 will begin
operation once the upper VCC UV threshold of 4.0V (typ) is reached.
RESTART CAPACITOR (LM5008-2 only)
The basic operation of the hiccup mode current limit is described in the functional description. In the LM25088-2
application example the RES pin is configured for delayed hiccup mode. Please refer to the functional description
to configure this pin in alternate configurations and also refer Figure 22 for the timing diagram. The delay time to
initiate a hiccup cycle (t1) is programmed by the selection of RES pin capacitor. In the case of continuous cycle-
by-cycle current limit detection at the CS pin, the time required for C
RES
to reach the 1.2V is given by
(22)
The cool down time (t2) is set by the time taken to discharge the RES cap with 1.2 µA current source. This
feature will reduce the input power drawn by the converter during a prolonged over current condition. In this
application 500 µs of delay time was selected. The minimum value of C
RES
capacitor should be no less than
0.022 µF.
MOSFET SELECTION
Selection of the Buck MOSFET is governed by the same tradeoffs as the switching frequency. Losses in power
MOSFETs can be broken down into conduction losses and switching losses. The conduction loss is given by:
P
DC
= D x (I
O
2
x R
DS(ON)
x 1.3) (23)
Where, D is the duty cycle and IO is the maximum load current. The factor 1.3 accounts for the increase in
MOSFET on-resistance due to heating. Alternatively, for a more precise calculation, the factor of 1.3 can be
ignored and the on-resistance of the MOSFET can be estimated using the R
DS(ON)
vs. Temperature curves in the
MOSFET datasheet.
The switching loss occurs during the brief transition period as the MOSFET turns on and off. During the transition
period both current and voltage are present in the MOSFET. The switching loss can be approximated as:
P
SW
= 0.5 x V
IN
x I
O
x (t
R
+ t
F
) x f
SW
where
• t
R
and t
F
are the rise and fall times of the MOSFET (24)
The rise and fall times are usually mentioned in the MOSFET datasheet or can be empirically observed on the
scope. Another loss, which is associated with the buck MOSFET is the “gate-charging loss”. This loss differs
from the above two losses in the sense that it is dissipated in the LM25088 and not in the MOSFET itself. Gate
charging loss, P
GC
, results from the current driving charging the gate capacitance of the power MOSFETs and is
approximated as:
P
GC
= VCC x Q
g
x f
SW
(25)
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