Datasheet
FB
L1
LM25085
PGATE
D1
GND
Q1
V
OUT
GND
5V
Pads for
wire loop
15 PH
R2
3.4k
47 PF
C6
R6
0.27:
47 PF
C7
R1
10k
4700 pF
C5
FB
L1
LM25085
PGATE
D1
GND
Q1
V
OUT
GND
5V
Pads for
wire loop
15 PH
C10
3300 pF
0.01 PF
R7
23.2k
R2
3.4k
C9
47 PF
C6
R6
0:
47 PF
C7
R1
10k
Output Ripple Control
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Figure 4. Minimum Ripple Using R7, C9, C10
8.2 Reduced Ripple Level Configuration
This configuration generates more ripple at V
OUT
than the above configuration, but uses one less capacitor.
If some ripple is acceptable in the application, this configuration is slightly more economical, and simpler.
R6 and C5 are used instead of R7, C9 and C10, as shown in Figure 5.
Ripple is generated at V
OUT
as the inductor’s ripple current flows through R6, and that ripple voltage is
passed to the FB pin via C5. The ripple at V
OUT
can be set as low as 25 mVp-p since it is not attenuated
by R1 and R2. The minimum value for R6 is calculated from Equation 10:
(10)
where, I
OR(min)
is the minimum inductor’s ripple current that occurs at minimum input voltage, and is 116
mAp-p at 5.5 V. The minimum value for R6 calculates to 0.22 Ωs. Using a standard value 0.27 Ω resistor
for R6, the ripple at V
OUT
ranges from 31 mVp-p to 292 mVp-p over the input voltage range, see Figure 11.
The minimum value for C5 is determined from Equation 11:
(11)
where, t
ON(max)
is the maximum on-time, 3479 ns in this evaluation board. The minimum value for C5
calculates to 4113 pF.
Figure 5. Reduced Ripple Configuration
6
AN-1905 LM25085 Evaluation Board SNVA375B–October 2008–Revised April 2013
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