Datasheet

Cff =
3 x t
ON(max)
(R
FB1
//R
FB2
)
R4 =
25 mV
I
OR(min)
LM25085, LM25085-Q1
www.ti.com SNVS593H –OCTOBER 2008–REVISED MARCH 2013
Figure 31. Current Limit vs. V
IN
(Circuit of Figure 32. LM25085 Power Dissipation (Circuit of
Figure 28) Figure 28)
Alternate Output Ripple Configurations
The minimum ripple configuration, using C1, C2 and R3, used in the example circuit, Figure 28, results in a low
ripple amplitude at V
OUT
determined mainly by the characteristics of the output capacitor and the ripple current in
L1. This configuration allows multiple ceramic capacitors to be used for V
OUT
if the output voltage is provided to
several places on the PC board. However, if a slightly higher level of ripple at V
OUT
is acceptable in the
application, and distributed capacitance is not used, the ripple required for the FB comparator pin can be
generated with fewer external components using the circuits shown below.
Reduced ripple configuration: In Figure 33, R3, C1 and C2 are removed (compared to Figure 28). A low value
resistor (R4) is added in series with C
OUT
, and a capacitor (Cff) is added across R
FB2
. Ripple is generated at
V
OUT
by the inductor’s ripple current flowing through R4, and that ripple voltage is passed to the FB pin via Cff.
The ripple at V
OUT
can be set as low as 25mVp-p since it is not attenuated by R
FB2
and R
FB1
. The minimum value
for R4 is calculated from:
where I
OR(min)
is the minimum ripple current, which occurs at minimum input voltage. The minimum value for Cff
is determined from:
where t
ON(max)
is the maximum on-time, which occurs at minimum VIN. The next larger standard value capacitor
should be used for Cff.
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