Datasheet

FB
LM25085
PGATE
GND
Q1
L1
C
OUT
R
FB2
R
FB1
V
OUT
GND
D1 R4
R4 =
V
RIP(min)
I
OR(min)
FB
LM25085
PGATE
GND
Q1
L1
Cff
C
OUT
R
FB2
R
FB1
V
OUT
GND
D1 R4
LM25085, LM25085-Q1
SNVS593H OCTOBER 2008REVISED MARCH 2013
www.ti.com
Figure 33. Reduced Ripple Configuration
Lowest cost configuration: This configuration, shown in Figure 34, is the same as Figure 33 except Cff is
removed. Since the ripple voltage at V
OUT
is attenuated by R
FB2
and R
FB1
, the minimum ripple required at V
OUT
is
equal to:
V
RIP(min)
= 25mV x (R
FB2
+ R
FB1
)/R
FB1
The minimum value for R4 is calculated from:
where I
OR(min)
is the minimum ripple current, which occurs at minimum input voltage.
Figure 34. Lowest Cost Ripple Generating Configuration
PC Board Layout
In most applications, the heat sink pad or tab of Q1 is connected to the switch node, i.e. the junction of Q1, L1
and D1. While it is common to extend the PC board pad from under these devices to aid in heat dissipation, the
pad size should be limited to minimize EMI radiation from this switching node. If the PC board layout allows, a
similarly sized copper pad can be placed on the underside of the PC board, and connected with as many vias as
possible to aid in heat dissipation.
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