Datasheet

LM25085
PGATE
ISEN
VCC
ADJ
C
ADJ
R
ADJ
Q1
D1
L1
LM25085
CURRENT LIMIT
COMPARATOR
GATE
DRIVER
40 PA
ADJ
R
ADJ
C
ADJ
40 PA
Q1
L1
D1
GATE
DRIVER
CURRENT LIMIT
COMPARATOR
ISEN
PGATE
VCC
R
SEN
+
-
+
-
USING Q1 R
DS(ON)
USING SENSE RESISTOR R
SEN
V
IN
V
IN
VIN
VIN
LM25085, LM25085-Q1
www.ti.com
SNVS593H OCTOBER 2008REVISED MARCH 2013
Figure 26. Current Limit Sensing
VCC REGULATOR
The VCC regulator provides a regulated voltage between the VIN and the VCC pins to provide the bias and gate
current for the PFET gate driver. The 0.47µF capacitor at the VCC pin must be a low ESR capacitor, preferably
ceramic as it provides the high surge current for the PFET’s gate at each turn-on. The capacitor must be located
as close as possible to the VIN and VCC pins to minimize inductance in the PC board traces.
Referring to Figure 7, the voltage across the VCC regulator (VIN VCC) is equal to VIN until VIN reaches
approximately 8.5V. At higher values of VIN, the voltage at the VCC pin is regulated at approximately 7.7V below
VIN. If VIN drops below about 8V due to voltage transients, the VCC pin can be pulled down below GND. To
prevent the negative VCC voltage from disturbing the internal circuit and causing abnormal operation, a Schottky
diode is recommended between VCC pin and GND pin. The VCC regulator has a maximum current capability of
at least 20mA. The regulator is disabled when the LM25085 is shutdown using the RT pin, or when the thermal
shutdown is activated.
PGATE DRIVER OUTPUT
The PGATE pin output swings between V
IN
(Q1 off) and the VCC pin voltage (Q1 on). The rise and fall times
depend on the PFET gate capacitance and the source and sink currents provided by the internal gate driver. See
Electrical Characteristics for the current capability of the driver.
P-CHANNEL MOSFET SELECTION
The PFET must be rated for the maximum input voltage, with some margin above that to allow for transients and
ringing which can occur on the supply line and the switching node. The gate-to-source voltage (V
GS
) normally
provided to the PFET is 7.7V for VIN greater than 8.5V. However, if the circuit is to be operated at lower values
of VIN, the selected PFET must be able to fully turn-on with a V
GS
voltage equal to VIN. The minimum input
operating voltage for the LM25085 is 4.5V.
Similar to NFETs, the case or exposed thermal pad for a PFET is electrically connected to the drain terminal.
When designing a PFET buck regulator the drain terminal is connected to the switching node. This situation
requires a trade-off between thermal and EMI performance since increasing the PC board area of the switching
node to aid the PFET power dissipation also increases radiated noise, possibly disrupting the circuit operation.
Typically the switching node area is kept to a reasonable minimum and the PFET peak current is derated to stay
within the recommended temperature rating of the PFET. The R
DS(ON)
of the PFET determines a portion of the
power dissipation in the PFET. However, PFETs with very low R
DS(ON)
usually have large values of gate charge.
A PFET with a higher gate charge has a corresponding slower switching speed, leading to higher switching
losses and affecting the PFET power dissipation.
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