Datasheet

FB
L1
LM25085A
PGATE
D1
GND
Q1
V
OUT
GND
1V
Pads for
wire loop
6.8 PH
R2
10k
68 PF
C6
R6
0.043:
R1
1.1k
3900 pF
C5
FB
L1
LM25085A
PGATE
D1
GND
Q1
V
OUT
GND
1V
Pads for
wire loop
6.8 PH
C10
3300 pF
0.01 PF
R7
48.7k
R2
10k
C9
R6
0:
68 PF
C6
R1
1.1k
www.ti.com Output Ripple Control
Figure 3. Minimum Ripple Using R7, C9, C10
B) Reduced Ripple Level Configuration: This configuration generates more ripple at V
OUT
than the
above configuration, but uses one less capacitor. If some ripple is acceptable in the application, this
configuration is slightly more economical, and simpler. R6 and C5 are used instead of R7, C9 and C10, as
shown in Figure 4.
Ripple is generated at V
OUT
as the inductor’s ripple current flows through R6, and that ripple voltage is
passed to the FB pin via C5. The ripple at V
OUT
can be set as low as 25 mVp-p since it is not attenuated
by R1 and R2. The minimum value for R6 is calculated from:
(10)
where I
OR(min)
is the minimum inductor’s ripple current, which occurs at minimum input voltage, and is 622
mAp-p at 4.5V. The minimum value for R6 calculates to 0.04 ohms. Using a standard value 43 mΩ
resistor for R6, the ripple at V
OUT
ranges from 27 mVp-p to 37 mVp-p over the input voltage range. See
Figure 10.
The minimum value for C5 is determined from:
(11)
Where t
ON(max)
is the maximum on-time, 1209 ns in this evaluation board. The minimum value for C5
calculates to 3660 pF.
Figure 4. Reduced Ripple Configuration
5
SNVA384B–February 2009–Revised April 2013 AN-1933 LM25085A Evaluation Board
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