Datasheet
LM25085A
SNVS601B –JANUARY 2009–REVISED MARCH 2013
www.ti.com
Electrical Characteristics (continued)
Limits in standard type are for T
J
= 25°C only; limits in boldface type apply over the junction temperature (T
J
) range of -40°C
to +125°C. Minimum and Maximum limits are specified through test, design, or statistical correlation. Typical values represent
the most likely parametric norm at T
J
= 25°C, and are provided for reference purposes only. Unless otherwise stated the
following conditions apply: VIN = 24V, R
T
= 100 kΩ.
Symbol Parameter Conditions Min Typ Max Units
RT Pin
RT
SD
Shutdown threshold RT Pin voltage rising 0.73 V
RT
HYS
Shutdown threshold hysteresis 50 mV
On-Time
t
ON – 1
On-time VIN = 4.5V, R
T
= 100 kΩ 3.5 5 7.15 µs
t
ON – 2
VIN = 24V, R
T
= 100 kΩ 560 720 870 ns
t
ON - 3
VIN = 42V, R
T
= 100 kΩ 329 415 500 ns
t
ON - 4
Minimum on-time in current limit
(3)
VIN = 24V, 25 mV overdrive at ISEN 55 140 235 ns
Off-Time
t
OFF(CL1)
Off-time (current limit)
(3)
VIN = 12V, V
FB
= 0V 5.56 8 10.96 µs
t
OFF(CL2)
VIN = 12V, V
FB
= 0.75V 2.59 3.7 5.16 µs
t
OFF(CL3)
VIN = 24V, V
FB
= 0V 9.03 13.2 18.1 µs
t
OFF(CL4)
VIN = 24V, V
FB
= 0.75V 4.29 6 8.54 µs
Regulation and Over-Voltage Comparators (FB Pin)
V
REF
FB regulation threshold 0.882 0.9 0.918 V
V
OV
FB over-voltage threshold Measured with respect to V
REF
350 mV
I
FB
FB bias current 10 nA
Soft-Start Function
t
SS
Soft-start time 1.16 1.8 3.15 ms
Thermal Shutdown
T
SD
Junction shutdown temperature Junction temperature rising 170 °C
T
HYS
Junction shutdown hysteresis 20 °C
Thermal Resistance
(4)
θ
JA
Junction to ambient, 0 LFPM air VSSOP-8 package 126 °C/W
flow
(5)
HVSSOP-PowerPAD-8 package 46
WSON-8 package 54
θ
JC
Junction to case, 0 LFPM air flow VSSOP-8 package 29 °C/W
(5)
HVSSOP-PowerPAD-8 package 5.5
WSON-8 package 9.1
(3) The tolerance of the minimum on-time (t
ON
-4) and the current limit off-times (t
OFF(CL1)
through (t
OFF(CL4)
) track each other over process
and temperature variations. A device which has an on-time at the high end of the range will have an off-time that is at the high end of its
range.
(4) For detailed information on soldering plastic VSSOP and WSON packages visit www.ti.com/packaging.
(5) Tested on a 4 layer JEDEC board. Four vias provided under the exposed pad. See JEDEC standards JESD51-5 and JESD51-7.
4 Submit Documentation Feedback Copyright © 2009–2013, Texas Instruments Incorporated
Product Folder Links: LM25085A