Datasheet

C
IN
+ C
BYP
=
I
OUT(max)
x t
ON(max)
'V
= 24.2 PF
5A x 1.21 Ps
0.25V
=
R3 x C1 =
(4.5V ± 0.49V) x 1.21 Ps
0.03V
= 1.62 x 10
-4
R3 x C1 =
(V
IN(min)
- V
A
) x t
ON
'V
LM25085A
www.ti.com SNVS601B –JANUARY 2009–REVISED MARCH 2013
components are determined using the following procedure:
Calculate V
A
= V
OUT
- (V
SW
x (1 – (V
OUT
/V
IN(min)
)))
where V
SW
is the absolute value of the voltage at the SW node during the off-time, typically 0.5V to 1V
depending on the diode D1. Using a typical value of 0.65V, V
A
calculates to 0.49V. V
A
is the nominal DC
voltage at the R3/C1 junction, and is used in the next equation:
where t
ON
is the maximum on-time (at minimum input voltage), and ΔV is the desired ripple amplitude at the
R3/C1 junction, typically 30 mVp-p. For this example
R3 and C1 are then selected from standard value components to produce the product calculated above.
Typical values for C1 are 3000 pF to 10,000 pF, and R3 is typically from 10 kΩ to 300 kΩ. C2 is then chosen
large compared to C1, typically 0.1 µF. For this example, 3300 pF is chosen for C1, requiring R3 to be 48.9
kΩ. A standard value 48.7 kΩ resistor is selected.
• C
IN
, C
BYP
: These capacitors limit the voltage ripple at VIN by supplying most of the switch current during the
on-time. At maximum load current, when Q1 is switched on, the current through Q1 suddenly increases to the
lower peak of the inductor’s ripple current, then ramps up to the upper peak, and then drops to zero at turn-
off. The average current during the on-time is the load current. For a worst case calculation, these capacitors
must supply this average load current during the maximum on-time, while limiting the voltage drop at VIN. For
this example, 0.25V is selected as the maximum allowable droop at VIN. Their minimum value is calculated
from:
A 33 µF electrolytic capacitor is selected for C
IN
, and a 1 µF ceramic capacitor is selected for C
BYP
. Due to
the ESR of C
IN
, the ripple at VIN will likely be higher than the calculation indicates, and therefore it may be
desirable to increase C
IN
to 47 µF or 68 µF. C
BYP
must be located as close as possible to the VIN and GND
pins of the LM25085A. The voltage rating for both capacitors must be at least 24V. The RMS ripple current
rating for the input capacitors must also be considered. A good approximation for the required ripple current
rating is I
RMS
> I
OUT
/2.
• D1: A Schottky diode is recommended. Ultra-fast recovery diodes are not recommended as the high speed
transitions at the SW pin may affect the regulator’s operation due to the diode’s reverse recovery transients.
The diode must be rated for the maximum input voltage, and the worst case current limit level. The average
power dissipation in the diode is calculated from:
P
D1
= V
F
x I
OUT
x (1-D)
where V
F
is the diode’s forward voltage drop, and D is the on-time duty cycle. Using Equation 1, the minimum
duty cycle occurs at maximum input voltage, and is calculated to be ≊4.2% in this example. The diode power
dissipation calculates to be:
P
D1
= 0.65V x 5A x (1- 0.042) = 3.11W
• C
VCC
: The capacitor at the VCC pin (from VIN to VCC) provides not only noise filtering and stability for the
VCC regulator, but also provides the surge current for the PFET gate drive. The typical recommended value
for C
VCC
is 0.47 µF. A good quality, low ESR, ceramic capacitor is recommended. C
VCC
must be located as
close as possible to the VIN and VCC pins. If the selected PFET has a Total Gate Charge specification of
100 nC or larger, or if the circuit is required to operate at input voltages below 7 volts, a larger capacitor may
be required. The maximum recommended value for C
VCC
is 1 µF.
• IC Power Dissipation: The maximum power dissipated in the LM25085A package is calculated using
Equation 12 at the maximum input voltage. The Total Gate Charge for the Si7465 PFET is specified to be 40
nC (max) in its data sheet. Therefore the total power dissipation within the LM25085A is calculated to be:
P
DISS
= 24V x ((40 nC x 200 kHz) + 1.25 mA) = 222 mW
Using an HVSSOP-PowerPAD-8 package with a θ
JA
of 46°C/W produces a temperature rise of 10°C from
junction to ambient.
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