Datasheet

a)
Delay Rising Edge Only
b)
Long delay at rising edge,
short delay at falling edge
c)
Short Delay at Rising Edge and
Long Delay at Falling Edge or
Equal Delays
GND
PGD
R
PG1
V
PGD
Power
Good
C
PG
GND
PGD
R
PG1
V
PGD
Power
Good
C
PG
GND
PGD
R
PG1
V
PGD
Power
Good
C
PG
R
PG2
R
PG2
LM25069
LM25069
LM25069
GND
PGD
R
PG
LM25069
V
PGD
Power
Good
VIN
UVLO
OVLO
GND
TIMER AND GATE
LOGIC CONTROL
LM25069
V
SYS
10k
R3
R4
Control
Restart
Shutdown/
20
A
20
A
1.17V
1.16V
LM25069
SNVS607E –FEBRUARY 2011–REVISED MARCH 2013 www.ti.com
V
OV(HYS)
= R3 x 20 µA (33)
Option C: The minimum UVLO level is obtained by connecting the UVLO pin to VIN as shown in Figure 33. Q1
is switched on when the VIN voltage reaches the POR threshold (≊2.6V). The OVLO thresholds are set using
R3, R4. Their values are calculated using the procedure in Option B.
Figure 33. UVLO = POR with Shutdown/Restart Control
Option D: The OVLO function can be disabled by grounding the OVLO pin. The UVLO thresholds are set as
described in Option B or Option C.
POWER GOOD PIN
During turn-on, the Power Good pin (PGD) is high until the voltage at VIN increases above ≊ 1.6V. PGD then
switches low, remaining low as the VIN voltage increases. When the voltage at OUT increases to within 1.3V of
the SENSE pin (V
DS
<1.3V), PGD switches high. PGD switches low if the V
DS
of Q1 increases above 1.9V. A
pull-up resistor is required at PGD as shown in Figure 34. The pull-up voltage (V
PGD
) can be as high as 17V, and
can be higher or lower than the voltages at VIN and OUT.
Figure 34. Power Good Output
If a delay is required at PGD, suggested circuits are shown in Figure 35. In Figure 35a, capacitor C
PG
adds delay
to the rising edge, but not to the falling edge. In Figure 35b, the rising edge is delayed by R
PG1
+ R
PG2
and C
PG
,
while the falling edge is delayed a lesser amount by R
PG2
and C
PG
. Adding a diode across R
PG2
(Figure 35c)
allows for equal delays at the two edges, or a short delay at the rising edge and a long delay at the falling edge.
Figure 35. Adding Delay to the Power Good Output Pin
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