Datasheet

t
RESTART
= C
T
x
7 x 0.72V
2.5 PA
7 x 0.72V
80 PA
1.42V
2.5 PA
++
C
T
=
t
FAULT
x 80 PA
1.42V
= t
FAULT
x 5.63 x 10
-5
C
T
=
t
FAULT
x 80 PA
1.72V
= t
FAULT
x 4.65 x 10
-5
C
T
=
t1 x 5.5 PA
1.72V
= t1 x 3.2 x 10
-6
LM25069
www.ti.com SNVS607E –FEBRUARY 2011–REVISED MARCH 2013
TIMER CAPACITOR, C
T
The TIMER pin capacitor (C
T
) sets the timing for the insertion time delay, fault timeout period, and restart timing
of the LM25069-2.
A) Insertion Delay - Upon applying the system voltage (V
SYS
) to the circuit, the external MOSFET (Q1) is held
off during the insertion time (t1 in Figure 23) to allow ringing and transients at V
SYS
to settle. Since each
backplane’s response to a circuit card plug-in is unique, the worst case settling time must be determined for each
application. The insertion time starts when VIN reaches the POR threshold, at which time the internal 5.5 µA
current source charges C
T
from 0V to 1.72V. The required capacitor value is calculated from:
(7)
For example, if the desired insertion delay is 250 ms, C
T
calculates to 0.8 µF. At the end of the insertion delay,
C
T
is quickly discharged by a 2 mA current sink.
B) Fault Timeout Period - During in-rush current limiting or upon detection of a fault condition where the current
limit and/or power limit circuits regulate the current through Q1, the fault timer current source (80 µA) switches on
to charge C
T
. The Fault Timeout Period is the time required for the voltage at the TIMER pin to transition from
ground to 1.72V, at which time Q1 is switched off. If the LM25069-1 is in use, the required capacitor value is
calculated from:
(8)
For example, if the desired Fault Timeout Period is 17 ms, C
T
calculates to 0.8 µF. When the Fault Timeout
Period expires, the LM25069-1 latches the GATE pin low until a power-up sequence is initiated by external
circuitry. If the LM25069-2 is in use, the Fault Timeout Period during restart cycles is approximately 18% shorter
than the initial fault timeout period which initiated the restart cycles since the voltage at the TIMER pin transitions
from 0.3V to 1.72V. Since the Fault Timeout Period must always be longer than the turn-on-time, the required
capacitor value for the LM25069-2 is calculated using this shorter time period:
(9)
For example, if the desired Fault Timeout Period is 17 ms, C
T
calculates to 0.96 µF. When the Fault Timeout
Period of the LM25069-2 expires, a restart sequence starts as described below (Restart Timiing). Since the
LM25069 normally operates in power limit and/or current limit during a power-up sequence, the Fault Timeout
Period MUST be longer than the time required for the output voltage to reach its final value. See the TURN-ON
TIME section
C) Restart Timing For the LM25069-2, after the Fault Timeout Period described above, C
T
is discharged by the
2.5 µA current sink to 1.0V. The TIMER pin then cycles through seven additional charge/discharge cycles
between 1V and 1.72V as shown in Figure 25. The restart time ends when the TIMER pin voltage reaches 0.3V
during the final high-to-low ramp. The restart time, after the Fault Timeout Period, is equal to:
= C
T
x 2.65 x 10
6
(10)
For example, if C
T
= 0.8 µF, t
RESTART
= 2.12 seconds. At the end of the restart time, Q1 is switched on. If the fault
is still present, the fault timeout and restart sequence repeats. The on-time duty cycle of Q1 is approximately
0.67% in this mode.
UVLO, OVLO
By programming the UVLO and OVLO thresholds the LM25069 enables the series pass device (Q1) when the
input supply voltage (V
SYS
) is within the desired operational range. If V
SYS
is below the UVLO threshold, or above
the OVLO threshold, Q1 is switched off, denying power to the load. Hysteresis is provided for each threshold.
Option A: The configuration shown in Figure 31 requires three resistors (R1-R3) to set the thresholds.
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