Datasheet
0
0
Drain Current
0
t1
0
0
t2
t3
a) Current Limit Only
V
SYS
V
DS
I
LIM
I
P
V
GATE
V
GSL
V
TH
t
ON
Source Voltage-toGate-
b) Power Limit and Current Limit
V
DS
Drain Current
t
ON
0
V
SYS
I
LIM
V
GATE
V
GSL
V
TH
t
ON
=
C
L
x V
SYS
2
2 x P
FET(LIM)
C
L
x P
FET(LIM)
2 x I
LIM
2
+
LM25069
SNVS607E –FEBRUARY 2011–REVISED MARCH 2013
www.ti.com
B) Turn-on with power limit and current limit: The maximum allowed power dissipation in Q1 (P
FET(LIM)
) is
defined by the resistor at the PWR pin, and the current sense resistor R
S
. See the POWER LIMIT THRESHOLD
section. If the current limit threshold (I
LIM
) is higher than the current defined by the power limit threshold at
maximum V
DS
(P
FET(LIM)/
V
SYS
) the circuit operates initially in the power limit mode when the V
DS
of Q1 is high,
and then transitions to current limit mode as the current increases to I
LIM
and V
DS
decreases. See Figure 30b.
Assuming the load (R
L
) is not connected during turn-on, the time for the output voltage to reach its final value is
approximately equal to:
(6)
For example, if V
SYS
= 12V, C
L
= 1000 µF, I
LIM
= 1A, and P
FET(LIM)
= 10W, t
ON
calculates to ≊12.2 ms, and the
initial current level (I
P
) is approximately 0.83A. The Fault Timeout Period must be set longer than t
ON
.
Figure 30. MOSFET Power Up Waveforms
MOSFET SELECTION
It is recommended that the external MOSFET (Q1) selection be based on the following criteria:
• The BV
DSS
rating should be greater than the maximum system voltage (V
SYS
), plus ringing and transients
which can occur at V
SYS
when the circuit card, or adjacent cards, are inserted or removed.
• The maximum continuous current rating should be based on the current limit threshold (50 mV/R
S
), not the
maximum load current, since the circuit can operate near the current limit threshold continuously.
• The Pulsed Drain Current spec (I
DM
) must be greater than the current threshold for the circuit breaker function
(95 mV/R
S
).
• The SOA (Safe Operating Area) chart of the device, and the thermal properties, should be used to determine
the maximum power dissipation threshold set by the R
PWR
resistor. The programmed maximum power
dissipation should have a reasonable margin from the maximum power defined by the FET's SOA chart if the
LM25069-2 is used since the FET will be repeatedly stressed during fault restart cycles. The FET
manufacturer should be consulted for guidelines.
• R
DS(on)
should be sufficiently low that the power dissipation at maximum load current (I
L(max)
2
x R
DS(on)
) does
not raise its junction temperature above the manufacturer’s recommendation.
If the circuit’s input voltage is at the low end of the LM25069’s operating range (<3.5V), or at the high end of the
operating range (>14V), the gate-to-source voltage applied to the MOSFET by the LM25069 is less than 5V, and
can approach 1V in a worst case situation. See the graph “ GATE Pin voltage”. The selected device must have a
suitable Gate-to-Source Threshold Voltage.
The gate-to-source voltage provided by the LM25069 can be as high as 19.5V at turn-on when the output voltage
is zero. At turn-off the reverse gate-to-source voltage will be equal to the output voltage at the instant the GATE
pin is pulled low. If the device chosen for Q1 is not rated for these voltages, an external zener diode must be
added from its gate to source, with the zener voltage less than the device maximum V
GS
rating. The zener
diode’s working voltage protects the MOSFET during turn-on, and its forward voltage protects the MOSFET
during shutoff. The zener diode’s forward current rating must be at least 260 mA to conduct the GATE pull-down
current when a circuit breaker condition is detected.
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