Datasheet

I
LIMIT
Load
Current
GATE
Pin
TIMER
Pin
1.72V
1V
1 2 3 7 8
2 mA
pulldown
20 PA
Gate Charge
80 PA
t
RESTART
Fault Timeout
Period
0.3V
Fault
Detection
2.5 PA
Restart
Control
VIN
UVLO/EN
OVLO
GND
R1
R2
R3
LM25069-1
V
SYS
LM25069
SNVS607E –FEBRUARY 2011–REVISED MARCH 2013 www.ti.com
Figure 24. Latched Fault Restart Control
The LM25069-2 provides an automatic restart sequence which consists of the TIMER pin cycling between 1.72V
and 1V seven times after the Fault Timeout Period, as shown in Figure 25. The period of each cycle is
determined by the 80 µA charging current, and the 2.5 µA discharge current, and the value of the capacitor C
T
.
When the TIMER pin reaches 0.3V during the eighth high-to-low ramp, the 20 µA current source at the GATE pin
turns on Q1. If the fault condition is still present, the Fault Timeout Period and the restart cycle repeat.
The Fault Timeout Period during restart cycles is approximately 18% shorter than the initial fault timeout period
which initiated the restart cycle. This is due to the fact that the TIMER pin transitions from 0.3V to 1.72V after
each restart time, rather than from ground.
Figure 25. Restart Sequence (LM25069-2)
Under-Voltage Lock-Out (UVLO)
The series pass MOSFET (Q1) is enabled when the input supply voltage (V
SYS
) is within the operating range
defined by the programmable under-voltage lockout (UVLO) and over-voltage lock-out (OVLO) levels. Typically
the UVLO level at V
SYS
is set with a resistor divider (R1-R3) as shown in Figure 21. Refering to the Block
Diagram when V
SYS
is below the UVLO level, the internal 20 µA current source at UVLO is enabled, the current
source at OVLO is off, and Q1 is held off by the 2 mA pull-down current at the GATE pin. As V
SYS
is increased,
raising the voltage at UVLO above its threshold the 20 µA current source at UVLO is switched off, increasing the
voltage at UVLO, providing hysteresis for this threshold. With the UVLO pin above its threshold, Q1 is switched
on by the 20 µA current source at the GATE pin if the insertion time delay has expired. See the Applications
Section for a procedure to calculate the values of the threshold setting resistors (R1-R3). The minimum possible
UVLO level at V
SYS
can be set by connecting the UVLO pin to VIN. In this case Q1 is enabled after the insertion
time.
Over-Voltage Lock-Out (OVLO)
The series pass MOSFET (Q1) is enabled when the input supply voltage (V
SYS
) is within the operating range
defined by the programmable under-voltage lockout (UVLO) and over-voltage lock-out (OVLO) levels. If V
SYS
raises the OVLO pin voltage above its threshold Q1 is switched off by the 2 mA pull-down current at the GATE
pin, denying power to the load. When the OVLO pin is above its threshold, the internal 20 µA current source at
OVLO is switched on, raising the voltage at OVLO to provide threshold hysteresis. When V
SYS
is reduced below
the OVLO level Q1 is enabled. See the Applications Section for a procedure to calculate the threshold setting
resistor values.
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