Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsPMICsPMIC - hot swap controller Multi-purpose VSSOP 10 Surface-mount

Power

Good

UVLO/EN

OVLO

PWR

GNDTIMER

PGD

OUT

VIN SENSE GATE

LM25069

OUT

SYS

LM25069

www.ti.com

SNVS607E –FEBRUARY 2011–REVISED MARCH 2013

LM25069 Positive Low Voltage Power Limiting Hot Swap Controller

Check for Samples: LM25069

FEATURES

APPLICATIONS

• Operating R ange: +2.9V to +17V

• Server Backplane Systems

• In-rush Current Limit for Safe Board Insertion • Base Station Power Distribution Systems

into Live Power Sources

• Solid State Circuit Breaker

• Programmable Maximum Power Dissipation in

the External Pass Device PACKAGE

• Adjustable Current Limit

• VSSOP-10

• Circuit Breaker Function for Severe Over-

DESCRIPTION

Current Events

The LM25069 positive hot swap controller provides

• Internal High Side Charge Pump and Gate

intelligent control of the power supply voltage to the

Driver for External N-channel MOSFET

load during insertion and removal of circuit cards from

• Adjustable Under-Voltage Lockout (UVLO) and

a live system backplane or other "hot" power sources.

Hysteresis

The LM25069 provides in-rush current control to limit

• Adjustable Over-Voltage Lockout (OVLO) and

system voltage droop and transients. The current limit

and power dissipation in the external series pass N-

Hysteresis

Channel MOSFET are programmable, ensuring

• Initial Insertion Timer Allows Ringing and

operation within the Safe Operating Area (SOA). The

Transients to Subside After System

POWER GOOD output indicates when the output

Connection

voltage is within 1.3V of the input voltage. The input

• Programmable Fault Timer Avoids Nuisance

under-voltage and over-voltage lockout levels and

Trips

hysteresis are programmable, as well as the initial

insertion delay time and fault detection time. The

• Active High Open Drain POWER GOOD Output

LM25069-1 latches off after a fault detection, while

• Available in Latched Fault and Automatic

the LM25069-2 automatically restarts at a fixed duty

Restart Versions

cycle. The LM25069 is available in a 10 pin VSSOP

package.

Typical Application

Figure 1. Positive Power Supply Control

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (29 pages)

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LM25069 www.ti.com SNVS607E – FEBRUARY 2011 – REVISED MARCH 2013 LM25069 Positive Low Voltage Power Limiting Hot Swap Controller Check for Samples: LM25069 FEATURES APPLICATIONS • • • • • 1 2 • • • • • • • • • • Operating R ange: +2.
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LM25069 SNVS607E – FEBRUARY 2011 – REVISED MARCH 2013 www.ti.com Connection Diagram SENSE 1 10 VIN 2 9 UVLO/EN 3 8 PGD OVLO 4 7 PWR GND 5 6 TIMER GATE OUT Figure 2. Top View 10-Lead VSSOP PIN DESCRIPTIONS Pin # Name Description Applications Information 1 SENSE Current sense input The voltage across the current sense resistor (RS) is measured from VIN to this pin. If the voltage across RS reaches 50mV the load current is limited and the fault timer activates.
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LM25069 www.ti.com SNVS607E – FEBRUARY 2011 – REVISED MARCH 2013 Absolute Maximum Ratings (1) (2) (3) VIN to GND (4) -0.3V to 20V SENSE, OUT, PGD to GND -0.3V to 20V UVLO to GND -0.3V to 20V OVLO to GND -0.3V to 20V VIN to SENSE -0.3V to +0.
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LM25069 SNVS607E – FEBRUARY 2011 – REVISED MARCH 2013 www.ti.com Electrical Characteristics (continued) Limits in standard type are for TJ = 25°C only; limits in boldface type apply over the junction temperature (TJ) range of -40°C to +85°C. Minimum and Maximum limits are ensured through test, design, or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only.
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LM25069 www.ti.com SNVS607E – FEBRUARY 2011 – REVISED MARCH 2013 Typical Performance Characteristics Unless otherwise specified the following conditions apply: TJ = 25°C, VIN = 12V VIN Pin Input Current vs. VIN SENSE Pin Input Current Figure 3. Figure 4. OUT Pin Input Current GATE Pin Voltage Figure 5. Figure 6. GATE Pin Source Current MOSFET Power Dissipation Limit Figure 7. Figure 8.
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LM25069 SNVS607E – FEBRUARY 2011 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) Unless otherwise specified the following conditions apply: TJ = 25°C, VIN = 12V 6 PGD Pin Low Voltage vs. Sink Current Input Current, Enabled vs. Temperature Figure 9. Figure 10. UVLO Threshold vs. Temperature UVLO Hysteresis Current vs. Temperature Figure 11. Figure 12. OVLO Threshold vs. Temperature OVLO Hysteresis Current vs. Temperature Figure 13. Figure 14.
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LM25069 www.ti.com SNVS607E – FEBRUARY 2011 – REVISED MARCH 2013 Typical Performance Characteristics (continued) Unless otherwise specified the following conditions apply: TJ = 25°C, VIN = 12V Current Limit Threshold vs. Temperature Circuit Breaker Threshold vs. Temperature Figure 15. Figure 16. Power Limit Threshold vs. Temperature GATE Output Voltage vs. Temperature Figure 17. Figure 18. GATE Source Current vs. Temperature PGD Low Voltage vs. Temperature Figure 19. Figure 20.
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LM25069 SNVS607E – FEBRUARY 2011 – REVISED MARCH 2013 www.ti.com Block Diagram LM25069 Charge Pump LDO Bias Circuit Breaker 95 mV 20 PA ID VIN GATE 2 mA SENSE 50 mV Current Limit 260 mA 19.5V Gate Control Current Limit/ Power Limit Control 1M VDS Power Limit OUT 5.5 PA Insertion Timer PGD 1.3V/ 1.9V 80 PA Fault Discharge TIMER Timer and Gate Logic Control 15 PA PWR 20 PA OVLO 1.16V 1.17V 2 mA End Insertion Time 2.5 PA Fault Discharge 1.72V 1.0V UVLO/EN 2.6V 20 PA 0.
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LM25069 www.ti.com SNVS607E – FEBRUARY 2011 – REVISED MARCH 2013 FUNCTIONAL DESCRIPTION The LM25069 is designed to control the in-rush current to the load upon insertion of a circuit card into a live backplane or other "hot" power source, thereby limiting the voltage sag on the backplane’s supply voltage, and the dV/dt of the voltage applied to the load. Effects on other circuits in the system are minimized, preventing possible unintended resets.
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LM25069 SNVS607E – FEBRUARY 2011 – REVISED MARCH 2013 www.ti.com If the TIMER pin voltage reaches 1.72V before in-rush current limiting or power limiting ceases (during t2), a fault is declared and Q1 is turned off. See the Fault Timer & Restart section for a complete description of the fault mode. VSYS UVLO V IN POR 5.5 PA TIMER Pin GATE Pin 1.72V 80 PA 2.5 PA 2 mA 260 mA pull-down 2 mA pull-down 20 PA source I LIMIT Load Current Output Voltage (OUT Pin) 1.
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LM25069 www.ti.com SNVS607E – FEBRUARY 2011 – REVISED MARCH 2013 If the in-rush limiting condition persists such that the TIMER pin reached 1.72V during t2, the GATE pin is then pulled low by the 2 mA pull-down current. The GATE pin is then held low until either a power up sequence is initiated (LM25069-1), or until the end of the restart sequence (LM25069-2). See the Fault Timer & Restart section.
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LM25069 SNVS607E – FEBRUARY 2011 – REVISED MARCH 2013 www.ti.com VSYS R1 VIN UVLO/EN Restart Control LM25069-1 R2 OVLO GND R3 Figure 24. Latched Fault Restart Control The LM25069-2 provides an automatic restart sequence which consists of the TIMER pin cycling between 1.72V and 1V seven times after the Fault Timeout Period, as shown in Figure 25. The period of each cycle is determined by the 80 µA charging current, and the 2.5 µA discharge current, and the value of the capacitor CT.
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LM25069 www.ti.com SNVS607E – FEBRUARY 2011 – REVISED MARCH 2013 Shutdown Control The load current can be remotely switched off by taking the UVLO pin below its threshold with an open collector or open drain device, as shown in Figure 26. Upon releasing the UVLO pin the LM25069 switches on the load current with in-rush current and power limiting. VSYS R1 VIN UVLO/EN Shutdown Control LM25069 R2 OVLO R3 GND Figure 26.
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LM25069 SNVS607E – FEBRUARY 2011 – REVISED MARCH 2013 www.ti.com HIGH CURRENT PATH FROM SYSTEM INPUT VOLTAGE TO MOSFET'S DRAIN SENSE RESISTOR RS SENSE VIN 3 4 10 LM25069 5 9 8 7 6 Figure 27. Sense Resistor Connections POWER LIMIT THRESHOLD The LM25069 determines the power dissipation in the external MOSFET (Q1) by monitoring the drain current (the current in RS), and the VDS of Q1 (SENSE to OUT pins).
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LM25069 www.ti.com SNVS607E – FEBRUARY 2011 – REVISED MARCH 2013 TURN-ON TIME The output turn-on time depends on whether the LM25069 operates in current limit, or in both power limit and current limit, during turn-on. A) Turn-on with current limit only: The current limit threshold (ILIM) is determined by the current sense resistor (RS).
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LM25069 SNVS607E – FEBRUARY 2011 – REVISED MARCH 2013 www.ti.com B) Turn-on with power limit and current limit: The maximum allowed power dissipation in Q1 (PFET(LIM)) is defined by the resistor at the PWR pin, and the current sense resistor RS. See the POWER LIMIT THRESHOLD section.
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LM25069 www.ti.com SNVS607E – FEBRUARY 2011 – REVISED MARCH 2013 TIMER CAPACITOR, CT The TIMER pin capacitor (CT) sets the timing for the insertion time delay, fault timeout period, and restart timing of the LM25069-2. A) Insertion Delay - Upon applying the system voltage (VSYS) to the circuit, the external MOSFET (Q1) is held off during the insertion time (t1 in Figure 23) to allow ringing and transients at VSYS to settle.
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LM25069 SNVS607E – FEBRUARY 2011 – REVISED MARCH 2013 www.ti.com VSYS VIN R1 LM25069 UVLO 1.17V R2 1.16V R3 20 PA TIMER AND GATE LOGIC CONTROL OVLO GND 20 PA Figure 31. UVLO and OVLO Thresholds Set By R1-R3 The procedure to calculate the resistor values is as follows: • Choose the upper UVLO threshold (VUVH), and the lower UVLO threshold (VUVL). • Choose the upper OVLO threshold (VOVH).
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LM25069 www.ti.com SNVS607E – FEBRUARY 2011 – REVISED MARCH 2013 VOVH = 1.16V x (R1 + R2 + R3) R3 (21) VOVL = [(R1 + R2) x ((1.16V) - 20 PA)] + 1.16V R3 (22) (23) VOV(HYS) = (R1 + R2) x 20 µA Option B: If all four thresholds must be accurately defined, the configuration in Figure 32 can be used. VSYS VIN 20 PA LM25069 R1 UVLO R3 1.17V R2 1.16V TIMER AND GATE LOGIC CONTROL OVLO R4 GND 20 PA Figure 32.
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LM25069 SNVS607E – FEBRUARY 2011 – REVISED MARCH 2013 www.ti.com VOV(HYS) = R3 x 20 µA (33) Option C: The minimum UVLO level is obtained by connecting the UVLO pin to VIN as shown in Figure 33. Q1 is switched on when the VIN voltage reaches the POR threshold (≊2.6V). The OVLO thresholds are set using R3, R4. Their values are calculated using the procedure in Option B. VSYS VIN 20 A LM25069 10k UVLO 1.17V Shutdown/ Restart Control TIMER AND GATE LOGIC CONTROL R3 1.
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LM25069 www.ti.com SNVS607E – FEBRUARY 2011 – REVISED MARCH 2013 Design-in Procedure The recommended design-in procedure is as follows: • Determine the current limit threshold (ILIM). This threshold must be higher than the normal maximum load current, allowing for tolerances in the current sense resistor value and the LM25069 Current Limit threshold voltage. Use equation 1 to determine the value for RS.
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LM25069 SNVS607E – FEBRUARY 2011 – REVISED MARCH 2013 www.ti.com GND VSYS To Load RS Q1 SENSE GATE OUT VIN UVLO PGD OVLO PWR GND TIMER R1 R2 R3 LM25069 PLUG-IN CARD CARD EDGE CONNECTOR Figure 36. Recommended Board Connector Design System Considerations a. Continued proper operation of the LM25069 hot swap circuit requires capacitance be present on the supply side of the connector into which the hot swap circuit is plugged in, as depicted in Figure 22.
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LM25069 www.ti.com SNVS607E – FEBRUARY 2011 – REVISED MARCH 2013 REVISION HISTORY Changes from Revision D (March 2013) to Revision E • Page Changed layout of National Data Sheet to TI format ..........................................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties.
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PACKAGE MATERIALS INFORMATION www.ti.com 8-Apr-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant LM25069PMM-1/NOPB VSSOP DGS 10 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LM25069PMM-2/NOPB VSSOP DGS 10 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LM25069PMME-1/NOPB VSSOP DGS 10 250 178.0 12.4 5.3 3.4 1.4 8.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 8-Apr-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM25069PMM-1/NOPB VSSOP DGS 10 1000 210.0 185.0 35.0 LM25069PMM-2/NOPB VSSOP DGS 10 1000 210.0 185.0 35.0 LM25069PMME-1/NOPB VSSOP DGS 10 250 210.0 185.0 35.0 LM25069PMME-2/NOPB VSSOP DGS 10 250 210.0 185.0 35.0 LM25069PMMX-1/NOPB VSSOP DGS 10 3500 367.0 367.0 35.
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