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8.4 OPTION D

The OVLO function can be disabled by removing the jumper from JMP1. The UVLO thresholds are set by

R1 and R4 using the procedure in option B above.

9 Shutdown

With the circuit in normal operation, the LM25069 can be shut down by grounding the UVLO pin. Test

point TP1, located next to JMP1, can be used for this purpose.

10 Power Good Output

The PGOOD logic output provides an indication of the circuit’s condition. This output is high when the

circuit is in normal operation - the OUT voltage is within 1.3V of the input. PGOOD is low when the circuit

is shutdown, either intentionally or due to a fault. PGOOD is also high when VIN is less than 1.6V.

This EVB is supplied with pins 1-2 jumpered on JMP2, powering the PGD pin from the input voltage

through a 100 kΩ pull-up resistor. To change the high level PGOOD voltage, move the jumper on JMP2 to

pins 2-3, and supply the appropriate pull-up voltage to terminal P1 (located next to JMP2). If the UVLO pin

is taken low to disable the LM25069, PGOOD switches low within 10 µs without waiting for the OUT

voltage to fall.

If a delay at the PGOOD output is desired, a resistor and capacitor can be added at positions R8 and C6.

11 LM25069-1 Latch Version

The LM25069-2 supplied on this evaluation board provides a restart attempt after a fault detection, as

described above. The companion Hot-Swap IC, the LM25069-1, latches off after a fault detection, with

external control required for restart. Restart is accomplished by momentarily taking the UVLO pin below its

threshold, or by removing and re-applying the input voltage at VIN. Contact the nearest Texas Instruments

sales office to obtain samples of the LM25069-1.

12 Performance Characteristics

Horizontal Resolution: 100 ms/div

Trace 1: V

, 10V/div

Trace 2: TIMER Pin, 1V/div

Trace 3: V

OUT

, 10V/div

= 12V, C

= 0.68 µF

Figure 8. Insertion Time Delay

AN-1947 LM25069 Evaluation Board SNVA388D–February 2009–Revised May 2013

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