Datasheet
I
LIMIT
Load
Current
GATE
Pin
TIMER
Pin
1.72V
1V
1 2 3 7 8
2 mA
pulldown
20 PA
Gate Charge
80 PA
t
RESTART
Fault Timeout
Period
0.3V
Fault
Detection
2.5 PA
www.ti.com
Fault Detection and Restart
7 Fault Detection and Restart
If the load current increases to the fault level (the current limit threshold, 5A), an internal current source
charges the timing capacitor at the TIMER pin. When the voltage at the TIMER pin reaches 1.72V, the
fault timeout period is complete, and the LM25069 shuts off Q1. The restart sequence then begins,
consisting of seven cycles at the TIMER pin between 1.72V and 1V, as shown in Figure 4. When the
voltage at the TIMER pin reaches 0.3V during the eighth high-to-low ramp, Q1 is turned on. If the fault is
still present, the fault timeout period and the restart sequence repeat.
Figure 4. Fault Timeout and Restart Sequence
The initial fault timeout period is equal to:
t
FAULT(Init)
= C
T
x 2.15 x 10
4
(4)
The restart fault timeout period is equal to:
t
FAULT(Restart)
= C
T
x 1.776 x 10
4
(5)
The restart time is equal to:
t
Restart
= C
T
x 2.65 x 10
6
(6)
The waveform at the TIMER pin can be monitored at the test pad located between C8 and R9. In this
evaluation board the initial fault timeout period is 14.6 ms, the restart fault timeout period is 12.1 ms, and
the restart time is 1.8 seconds. See Figure 11, Figure 12, and Figure 13.
8 UVLO/OVLO Input Voltage Thresholds
As supplied, the input voltage UVLO thresholds on this evaluation board are approximately 4.8V
increasing, and 4.5V decreasing. The OVLO thresholds are approximately 15V increasing, and 14.6V
decreasing. The four thresholds are determined by resistors R1-R4. The threshold at the UVLO pin is
1.17V, and is 1.16V at the OVLO pin, and internal 20 µA current sources provide hysteresis for each
threshold. See the LM25069 Positive Low Voltage Power Limiting Hot Swap Controller (SNVS607 for
more details.
8.1 Option A
This evaluation board is supplied with the jumper at JMP1 on pins 2-3, resulting in the configuration shown
in Figure 5.
5
SNVA388D–February 2009–Revised May 2013 AN-1947 LM25069 Evaluation Board
Submit Documentation Feedback
Copyright © 2009–2013, Texas Instruments Incorporated