Datasheet

P
FET(LIM)
=
2.32 x 10
5
x R10
R9
Board Connections/Startup www.ti.com
5 Board Connections/Startup
The input voltage source is connected to the J1 connector, and the load is connected to the J2 connector
at the OUT and GND terminals. USE TWISTED WIRES. A voltmeter should be connected to the input
terminals, and one to the output terminals. The input current can be monitored with an ammeter or current
probe. To monitor the status of the PGD output, connect a voltmeter from PGOOD to GND on the J2
terminal block. Put the toggle switch in the ON position.
Increase the input voltage gradually. The input current should remain less than 2 mA until the upper UVLO
threshold is reached. When the threshold is reached, Q1 is turned on. If viewed on an oscilloscope, the
input current increases as shown in Figure 3 before settling at the value defined by the load. The turn-on
timing depends on the input voltage, power limit setting, current limit setting, and the final load current,
and is between ≊3.0 ms with no load current, and ≊6.5 ms with a 3.7A load current, with VIN = 14V. See
Figure 9 and Figure 10.
6 Circuit Parameter Changes
6.1 Current Limit
The current limit threshold is set by R10 according to the following equation:
I
LIM
= 50 mV/R10 (1)
If the load current increases such that the voltage across R10 reaches 50 mV, the LM25069 then
modulates Q1’s gate to limit the current to that level. This evaluation board is supplied with a 10 mohm
resistor for R10, resulting in a current limit of 5A. To change the current limit threshold replace R10 with a
resistor of the required value and power capability.
6.2 Power Limit
The maximum power dissipated in Q1 during turn-on, or due to a fault, is limited by R9 and R10 according
to the following equation:
(2)
With the components supplied on the evaluation board, P
FET(LIM)
= 15W. During turn-on, when the voltage
across Q1 is high, its gate is modulated to limit its drain current so the power dissipated in Q1 does not
exceed 15W. As the drain-to-source voltage decreases, the drain current increases, maintaining the power
dissipation constant. When the drain current reaches the current limit threshold set by R10, the current is
then maintained constant until the output voltage reaches its final value. The current then decreases to a
value determined by the load. See Figure 3, Figure 9, and Figure 10.
Each time Q1 is subjected to the maximum power limit conditions it is internally stressed for a few
milliseconds. For this reason, the power limit threshold must be set lower than the limit indicated by the
FET’s SOA chart. In this evaluation board, the power limit threshold is set at 15W, compared to ≊40W limit
indicated in the Fairchild FDD8874 data sheet. The FET manufacturer should be contacted for more
information on this subject.
6.3 Insertion Time
The insertion time starts when the input voltage at VIN reaches 2.6V, and its duration is equal to
t
INSERTION
= C8 x 3.13 x 10
5
(3)
During the insertion time, Q1 is held off regardless of the voltage at VIN. This delay allows ringing and
transients at VIN subside before the input voltage is applied to the load via Q1. The insertion time on this
evaluation board is ≊213 ms. See Figure 8.
4
AN-1947 LM25069 Evaluation Board SNVA388D–February 2009–Revised May 2013
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