Datasheet

UVLO/EN
OVLO
R1
R2
R3
R4
TP1
PGD
V
PGD
TIMER PWR
GND
LM25069
14k
N/U
3.48k
1.47k
R7
100k
R8
0:
C6
Open
C8
0.68 PF
R9
8
5
7
6
4
3
34.8k
TP
VIN SENSE GATE OUT
FDD8874
Q1
PGD
V
IN
GND
+2.9V to +17V
V
OUT
C1
1000 pF
Z1
16V
R10
0.01:
C3 C4
220 PF
35V
220 PF
35V
GND
C5
0.1 PF
2
1 10
9
P1
1
2
3
JMP2
1
2 3
JMP1
C7
100 PF
35V
BACKPLANE
HOT SWAP CIRCUIT
SW1
Theory of Operation www.ti.com
For a hot swap circuit to function reliably, capacitance is needed on the supply side of the system
connector (C7). Its purpose is to minimize voltage transients which occur whenever the load current
changes or is shut off. If the capacitance is not present, wiring inductance in the supply lines generate a
voltage transient at shutoff which can exceed the absolute maximum rating of the LM25069, resulting in its
destruction.
The LM25069EVB is supplied with pins 2-3 jumpered on JMP1, and pins 1-2 jumpered on JMP2.
Figure 2. Evaluation Board Schematic
3 Theory of Operation
The LM25069 provides intelligent control of the power supply connections of a load which is to be
connected to a live power source. The two primary functions of a hot swap circuit are in-rush current
limiting during turn-on, and monitoring of the load current for faults during normal operation. Additional
functions include Under-Voltage Lock-Out (UVLO) and Over-Voltage Lock-Out (OVLO) to ensure voltage
is supplied to the load only when the system input voltage is within a defined range, power limiting in the
series pass FET (Q1) during turn-on, and a Power Good logic output (PGD) to indicate the circuit status.
Upon applying the input voltage to the LM25069 (e.g., SW1 is switched on), Q1 is initially held off for the
insertion delay (≊213 ms) to allow ringing and transients at the input to subside. At the end of the insertion
delay, if the input voltage at VIN is between the UVLO and OVLO thresholds, Q1 is turned on in a
controlled manner to limit the in-rush current. If the in-rush current were not limited during turn-on, the
current would be high (very high!) as the load capacitors (C3, C4) charge up, limited only by the surge
current capability of the voltage source, C7’s characteristics, and the wiring resistance (a few milliohms).
That very high current could damage the edge connector, PC board traces, and possibly the load
capacitors receiving the high current. Additionally, the dV/dt at the load’s input is controlled to reduce
possible EMI problems.
The LM25069 limits in-rush current to a safe level using a two step process. In the first portion of the turn-
on cycle, when the voltage differential across Q1 is highest, Q1’s power dissipation is limited to a peak of
15W by monitoring its drain current (the voltage across R10) and its drain-to-source voltage. Their product
is maintained constant by controlling the drain current as the drain-to-source voltage decreases (as the
output voltage increases). This is shown in the constant power portion of Figure 3 where the drain current
2
AN-1947 LM25069 Evaluation Board SNVA388D–February 2009–Revised May 2013
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