Datasheet

SCL
V
IH
V
IL
V
IH
V
IL
P S
S P
SDA
t
HD;DAT
t
SU;STO
t
HD;STA
t
SU;STA
t
SU;DAT
t
HIGH
t
BUF
t
LOW
t
R
t
F
LM25066I, LM25066IA
www.ti.com SNVS824C –JUNE 2012–REVISED MARCH 2013
Table 47. Device Addressing (continued)
ADR2 ADR1 ADR0 Decoded Address
0 1 Z 17h
0 1 0 50h
0 1 1 51h
1 Z Z 52h
1 Z 0 53h
1 Z 1 54h
1 0 Z 55h
1 0 0 56h
1 0 1 57h
1 1 Z 58h
1 1 0 59h
1 1 1 5Ah
SMBus Communications Timing Requirements
Figure 50. SMBus Timing Diagram
Table 48. SMBus Timing Definition
Symbol Parameter Limits Unit Comments
Min Max
F
SMB
SMBus Operating Frequency 10 400 kHz
T
BUF
Bus free time between Stop and Start Condition 1.3 µs
T
HD:STA
Hold time after (Repeated) Start Condition. After this 0.6 µs
period, the first clock is generated.
T
SU:STA
Repeated Start Condition setup time 0.6 µs
T
SU:STO
Stop Condition setup time 0.6 µs
T
HD:DAT
Data hold time 300 ns
T
SU:DAT
Data setup time 100 ns
T
TIMEOUT
Clock low time-out 25 35 ms
(1)
T
LOW
Clock low period 1.5 µs
T
HIGH
Clock high period 0.6 µs
(2)
(1) Devices participating in a transfer will timeout when any clock low exceeds the value of T
TIMEOUT,MIN
of 25 ms. Devices that have
detected a timeout condition must reset the communication no later than T
TIMEOUT,MAX
of 35 ms. The maximum value must be adhered
to by both a master and a slave as it incorporates the cumulative stretch limit for both a master (10ms) and a slave (25ms).
(2) T
HIGH MAX
provides a simple method for devices to detect bus idle conditions.
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