Datasheet

LM25066I/A
Inductive
Load
VIN
GND
+12V
GND
LIVE
POWER
SOURCE
PLUG-IN BOARD
OUT
R
S
Q
1
V
OUT
SENSE
TVS
D1
Schottky
D2
V
SYS
GATE
C
L
LM25066I, LM25066IA
SNVS824C –JUNE 2012–REVISED MARCH 2013 www.ti.com
B) If the load powered by the LM25066I/A hot-swap circuit has inductive characteristics, a Schottky diode is
required across the LM25066I/A’s output along with some load capacitance. The capacitance and diode are
necessary to limit the negative excursion at the OUT pin when the load current is shut off. If the OUT pin
transitions more than 0.3V negative, the LM25066I/A will internally reset, erasing the volatile setting for retries
and warning thresholds. See Figure 47. To alleviate this, a small gate resistance (e.g. 10Ω) can be used. This
resistor has the added benefit of damping any high frequency gate voltage oscillations, particularly in paralleled
FET arrangements.
Figure 47. Output Diode Required for Inductive Loads
PC BOARD GUIDELINES
The following guidelines should be followed when designing the PC board for the LM25066I/A:
• Place the LM25066I/A close to the board’s input connector to minimize trace inductance from the connector
to the MOSFET.
• Place a small capacitor, C
IN
(1nF), directly adjacent to the VIN and GND pins of the LM25066I/A to help
minimize transients which may occur on the input supply line. Transients of several volts can easily occur
when the load current is shut off. ASIDE: note that if the current drawn by such capacitor is deemed
unacceptable, input voltage spike transients can be appropriately miniminzed by proper placement of a TVS
device and operation without this C
IN
capacitor becomes feasible.
• Place a 1 µF capacitor as close as possible to VREF pin.
• Place a 1 µF capacitor as close as possible to VDD pin.
• The sense resistor (R
S
) should be placed close to the LM25066I/A. In particular, the trace to the VIN pin
should be made as low resistance as practical to ensure maximum current and power measurement
accuracy. Connect R
S
using the Kelvin techniques shown in Figure 37.
• The high current path from the board’s input to the load (via Q
1
) and the return path should be parallel and
close to each other to minimize parasitic loop inductance.
• The ground connections for the various components around the LM25066I/A should be connected directly to
each other and to the LM25066I/A’s GND pin and then connected to the system ground at one point. Do not
connect the various component grounds to each other through the high current ground line. For more details,
see application note AN-2100 SNVA464.
• Provide adequate heat sinking for the series pass device (Q
1
) to help reduce stresses during turn-on and
turn-off.
• Keep the gate trace from the LM25066I/A to the pass MOSFET short and direct.
• The board’s edge connector can be designed such that the LM25066I/A detects via the UVLO/EN pin that the
board is being removed and responds by turning off the load before the supply voltage is disconnected. For
example, in Figure 48, the voltage at the UVLO/EN pin goes to ground before V
SYS
is removed from the
LM25066I/A because of the shorter edge connector pin. When the board is inserted into the edge connector,
the system voltage is applied to the LM25066I/A’s VIN pin before the UVLO voltage is taken high, thereby
allowing the LM25066I/A to turn on the output in a controlled fashion.
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