Datasheet
GND
LM25066I/A
R
PG1
V
PGD
C
PG
PGD
GND
LM25066I/A
R
PG1
Power
Good
V
PGD
C
PG
PGD
R
PG2
GND
LM25066I/A
R
PG1
V
PGD
C
PG
PGD
R
PG2
C) Short Delay at Rising Edge and
Long Delay at Falling Edge or
Equal Delays
B) Long Delay at Rising Edge,
Short Delay at Falling Edge
A) Delay at Rising Edge Only
Power
Good
Power
Good
GND
LM25066I/A
R
PG
Power Good
V
PGD
OUT
FB
GND
PGD
GATE
from UVLO
from OVLO
1.167V
Q1
V
OUT
R4
R5
LM25066I/A
24uA
LM25066I, LM25066IA
www.ti.com
SNVS824C –JUNE 2012–REVISED MARCH 2013
Figure 44. Programming the PGD Threshold
Figure 45. Power Good Output
Figure 46. Adding Delay to the Power Good Output Pin
SYSTEM CONSIDERATIONS
A) Continued proper operation of the LM25066I/A hot-swap circuit normally dictates that capacitance be present
on the supply side of the connector into which the hot-swap circuit is plugged in, as depicted in Figure 47. The
capacitor in the “LIVE POWER SOURCE” section is necessary to absorb the transient generated whenever the
hot-swap circuit shuts off the load current. If the capacitance is not present, parasitic inductance of the supply
lines will generate a voltage transient at shut-off which may exceed the absolute maximum rating of the
LM25066I/A, resulting in its destruction. A TVS device with appropriate voltage and power ratings can also be
connected from VIN to GND to clamp the voltage spike (see application note AN-2100 SNVA464).
Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback 29
Product Folder Links: LM25066I LM25066IA