Datasheet

V
PGDL
= 1.167V + [R4 x (1.167V + 24 PA)]
R5
V
PGDH
=
1.167V x (R4 + R5)
R5
V
PGD(HYS)
= R4 x 24 PA
R4 =
V
PGDH
- V
PGDL
24 PA
=
V
PGD(HYS)
24 PA
R5 =
1.167V x R4
(V
PGDH
- 1.167V)
VIN
UVLO/EN
OVLO
GND
10k
R3
R4
1.16V
1.16V
TIMER AND
GATE
LOGIC CONTROL
LM25066I/A
V
SYS
23 A
23 A
LM25066I, LM25066IA
SNVS824C JUNE 2012REVISED MARCH 2013
www.ti.com
Figure 43. UVLO = POR
Option D: The OVLO function can be disabled by grounding the OVLO pin. The UVLO thresholds are set as
described in Option B or Option C.
POWER GOOD
When the voltage at the FB pin increases above its threshold, the internal pulldown acting on the PGD pin is
disabled allowing PGD to rise to V
PGD
through the pullup resistor, R
PG
, as shown in Figure 45. The pullup voltage
(V
PGD
) can be as high as 17V, and can be higher or lower than the voltages at VIN and OUT. VDD is a
convenient choice for V
PGD
as it allows interface to low voltage logic and avoids glitching on PGD during power-
up. If a delay is required at PGD, suggested circuits are shown in Figure 46 In Figure 46A, capacitor C
PG
adds
delay to the rising edge, but not to the falling edge. In Figure 46B, the rising edge is delayed by R
PG1
+ R
PG2
and
C
PG
, while the falling edge is delayed a lesser amount by R
PG2
and C
PG
. Adding a diode across R
PG2
(Figure 46C) allows for equal delays at the two edges, or a short delay at the rising edge and a long delay at the
falling edge.
Setting the output threshold for the PGD pin requires two resistors (R4, R5) as shown in Figure 44. While
monitoring the output voltage is shown in Figure 44. R4 can be connected to any other voltage which requires
monitoring.
The resistor values are calculated as follows:
Choose the upper and lower threshold (V
PGDH
) and (V
PGDL
) at V
OUT
.
(34)
As an example, assume the application requires the following thresholds: V
PGDH
= 10.14V, and V
PGDL
= 9.9V.
Therefore V
PGD(HYS)
= 0.24V. The resistor values are:
R4 = 10 k, R5 = 1.3 k
Where the R4 and R5 resistor values are known, the threshold voltages and hysteresis are calculated from the
following:
(35)
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