Datasheet

t
RESTART
= C
T
x
7 x 0.7V
2.8 PA
7 x 0.7V
90 PA
1.4V
2.8 PA
++
C
T
=
t
FAULT
x 90 PA
1.7V
= t
FAULT
x 5.3 x 10
-5
C
T
=
t
1
x 5.5 PA
1.7V
= t
1
x 3.2 x 10
-6
LM25066I, LM25066IA
www.ti.com SNVS824C –JUNE 2012–REVISED MARCH 2013
A) Insertion Delay -Upon applying the system voltage (V
SYS
) to the circuit, the external MOSFET (Q
1
) is held off
during the insertion time (t
1
in Figure 32) to allow ringing and transients at V
SYS
to settle. Since each backplane’s
response to a circuit card plug-in is unique, the worst case settling time must be determined for each application.
The insertion time starts when VIN reaches the POR threshold, at which time the internal 5.5 µA current source
charges C
T
from 0V to 1.7V. The required capacitor value is calculated from:
(7)
For example, if the desired insertion delay is 250 ms, C
T
calculates to 0.8 µF. At the end of the insertion delay,
C
T
is quickly discharged by a 1.9 mA current sink.
B) Fault Timeout Period -During inrush current limiting or upon detection of a fault condition where the current
limit and/or power limit circuits regulate the current through Q
1
, the fault timer current source (90 µA) is switched
on to charge C
T
. The Fault Timeout Period is the time required for the TIMER pin voltage to reach 1.7V, at which
time Q
1
is switched off. The required capacitor value for the desired Fault Timeout Period t
FAULT
is calculated
from:
(8)
For example, if the desired Fault Timeout Period is 15 ms, C
T
calculates to 0.8 µF. C
T
is discharged by the 2.8
µA current sink at the end of the Fault Timeout Period. After the Fault Timeout Period, if retry is disabled, the
LM25066I/A latches the GATE pin low until a power up sequence is initiated by external circuitry. When the Fault
Timeout Period of the LM25066I/A expires, a restart sequence starts as described below (Restart Timing).
During consecutive cycles of the restart sequence, the fault timeout period is shorter than the initial fault timeout
period described above by approximately 20% since the voltage at the TIMER pin starts ramping up from 0.3V
rather than ground.
Since the LM25066I/A normally operates in power limit and/or current limit during a power up sequence, the
Fault Timeout Period MUST be longer than the time required for the output voltage to reach its final value. See
TURN-ON TIME.
C) Restart Timing - For the LM25066I/A, after the Fault Timeout Period described above, C
T
is discharged by
the 2.8 µA current sink to 1V. The TIMER pin then cycles through seven additional charge/discharge cycles
between 1V and 1.7V as shown in Figure 34. The restart time ends when the TIMER pin voltage reaches 0.3V
during the final high-to-low ramp. The restart time, after the Fault Timeout Period, is equal to:
(9)
= C
T
x 2.3 x 10
6
(10)
For example, if C
T
= 0.8 µF, t
RESTART
= 2 seconds. At the end of the restart time, Q
1
is switched on. If the fault is
still present, the fault timeout and restart sequence repeats. The on-time duty cycle of Q
1
is approximately 0.67%
in this mode.
UVLO, OVLO
By programming the UVLO and OVLO thresholds the LM25066I/A enables the series pass device (Q
1
) when the
input supply voltage (V
SYS
) is within the desired operational range. If V
SYS
is below the UVLO threshold, or above
the OVLO threshold, Q
1
is switched off, denying power to the load. Hysteresis is provided for each threshold.
Option A: The configuration shown in Figure 41 requires three resistors (R1-R3) to set the thresholds.
Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback 25
Product Folder Links: LM25066I LM25066IA